MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 546

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Universal Serial Bus Interface
24.9.9.4
Once the host controller has idled itself using the empty schedule detection, it naturally activates and
begins processing from the Periodic Schedule at the beginning of each micro-frame. In addition, it may
have idled itself early in a micro-frame. When this occurs (idles early in the micro-frame) the host
controller must occasionally reactivate during the micro-frame and traverse the asynchronous schedule to
determine whether any progress can be made. Asynchronous schedule Start Events are defined to be:
24.9.9.5
The operation of the empty asynchronous schedule detection feature depends on the proper management
of the Reclamation bit in the USBSTS register. The host controller tests for an empty schedule just after it
fetches a new queue head while traversing the asynchronous schedule. The host controller sets the
Reclamation bit whenever an asynchronous schedule traversal Start Event occurs. The Reclamation bit is
also set whenever the host controller executes a transaction while traversing the asynchronous
schedule.The host controller clears the Reclamation bit whenever it finds a queue head with its H-bit set.
The software should only set a queue head's H-bit if the queue head is in the asynchronous schedule. If the
software sets the H-bit in an interrupt queue head, the resulting behavior is undefined. The host controller
may clear the Reclamation bit when executing from the periodic schedule.
24.9.10 Managing Control/Bulk/Interrupt Transfers via Queue Heads
This section presents an overview of how the host controller interacts with queuing data structures.
Queue heads use the Queue Element Transfer Descriptor (qTD) structure defined in
“Queue Element Transfer Descriptor (qTD).”
24-84
•
•
AsyncListAddr
Operational
Whenever the host controller transitions from the periodic schedule to the asynchronous schedule.
If the periodic schedule is disabled and the asynchronous schedule is enabled, then the beginning
of the micro-frame is equivalent to the transition from the periodic schedule, or
The asynchronous schedule traversal restarts from a sleeping state.
Registers
USBCMD
USBSTS
•
•
•
•
•
•
Figure 24-50. Asynchronous Schedule List with Annotation to Mark Head of List
Asynchronous Schedule Traversal: Start Event
Reclamation Status Bit (USBSTS Register)
H
1
Horizontal Ptr
Reclamation Flag
List Head
Operational
Area
MCF5253 Reference Manual, Rev. 1
Typ T
01
1: Transaction Executed
0: Head of List Seen
0
Asynchronous Schedule
H
0
Horizontal Ptr
Operational
Area
Typ T
01 0
H
0
Horizontal Ptr
Freescale Semiconductor
Operational
Section 24.8.5,
Area
Typ T
01 0