MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 192

IC MPU 32BIT 140MHZ 225-MAPBGA

MCF5253CVM140

Manufacturer Part Number
MCF5253CVM140
Description
IC MPU 32BIT 140MHZ 225-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF525xr

Specifications of MCF5253CVM140

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
140MHz
Connectivity
CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
Peripherals
DMA, WDT
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
225-MAPBGA
Family Name
MCF5xxx
Device Core
ColdFire V2
Device Core Size
32b
Frequency (max)
140MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.2/3.3V
Operating Supply Voltage (max)
1.32/3.6V
Operating Supply Voltage (min)
1.08/3V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
225
Package Type
MA-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant

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General Purpose Timer Modules
11.6.5
There are two timers on the MCF5253. With a 70 MHz clock, the maximum period is 3.83 seconds and a
resolution of 14.3 ns. The timers can be free running or count to a value and reset. The following examples
set up the timers:
Timer0 will count to $AFAF, toggle its output, and reset back to $0000. This will continue infinitely until
the timer is disabled or a reset occurs. No interrupts are set. Prescale is set at 256 and the system clock is
divided by 16, therefore resolution is (16 × (256))/70 MHz = 58.51us. Timeout period is
(16 × 256 × 44976)/70 MHz = 2.63s ($0 - $AFAF = 44976 decimal).
Autovectors and ICRs have been set up as follows. The interrupt levels and priorities were chosen by
random for demonstrative purposes. Users should define the interrupt level and priorities for their specific
application.
11.6.5.1
Bits 15:8 sets the prescale to 256 ($FF)
Bits 7:6 set for no interrupt (“00”)
Bits 5:4 sets output mode for “toggle”. No interrupts(“10”)
Bits 3 set for “restart” (“1”)
Bits 2:1 set the clocking source to system clock/16 (“10”)
Bit 0 enables/disables the timer (“0”)
11.6.5.2
The TRR register is set to $AFAF. The timer will count up to this value (TCN = TRR), toggle the “TOUT”
pin, and reset the TCN to $0000.
Other registers used for TIMER 0
TCR0;TIMER0 Capture Register, 16-bit, R
TER0;TIMER0 Event Register, 8-bit, R/W
11-6
move.w #$FF2C,D0;Setup the Timer mode register (TMR0)
move.w D0,TMR1;
move.w #$0000,D0; writing to the timer counter with any value resets it to zero
move.w D0,TCN1;
move.w #$AFAF,D0;Setup the Timer reference register (TRR0)
move.w D0,TRR1
Timer Initialization Example Code
Timer0 (Timer Mode Register)
Timer0 (Timer Reference Register0)
The timers were initialized in the SIM to have interrupt values. The
following examples have the interrupts disabled. The initialization in the
SIM configuration was for reference. The Timers CANNOT provide
interrupt vectors, only autovectors.
MCF5253 Reference Manual, Rev. 1
NOTE
Bit 1 is set to 0 to disable the timer
Freescale Semiconductor

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