MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 134

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Bus Operation
terminate in an error. If a match is found for any chip selects or DRAM, the bus cycle will be executed on
the external bus. Chip select accesses follow timing diagrams given in this section. DRAM accesses are
different. They are described in the section on the DRAM controller.
Table 8-5
Basic operation of the MCF5253 bus is a three-clock bus cycle. During the first clock, the address is
driven. CSx is asserted at the falling edge of the clock to indicate that address and attributes are valid and
stable. Data and TA are sampled during the second clock of a bus-read cycle. TA is generated internally in
the chip select module.
During a read, the external device provides data and is sampled at the rising edge at the end of the second
bus clock. This data is concurrent with TA, which is also sampled at the rising edge of the clock. During
a write, the MCF5253 drives data from the rising clock edge at the end of the first clock to the rising clock
edge at the end of the bus cycle.
Users can add wait states between the first and second clocks by delaying the assertion of TA. This refers
to internal transfers only and not the write cycles. This is done by programming the relevant chip select
registers. If “0000” is programmed in the WS field of the relevant chip select register, a no wait cycle
results. If n is programmed in the WS field, n wait cycles will result. The last clock of the bus cycle uses
what would be an idle clock between cycles to provide hold time for address and write data.
and
8.5.2
The Read cycle as shown in
Register (CSR) is programmed to value “0000”. The CS low time is increased with n clocks if n is
programmed into the WS field.
During a read cycle, the MCF5253 receives data from memory or from a peripheral device. The read cycle
flowchart is shown in
8-6
Matches
KRAM
Figure 8-6
yes
no
no
no
no
no
shows the type of access as a function of match in various memory space programming registers.
Read Cycle
show the basic read and write operations.
Matches
SBC 2
any
yes
no
no
no
no
Figure 8-3
All other combinations
Figure
Matches
SBC 1
any
any
yes
while the read cycle timing diagram is shown in
no
no
no
8-3, will occur if the wait cycle field (WS) in the Chip Select Control
Table 8-5. Accesses by Matches
MCF5253 Reference Manual, Rev. 1
Chip Selects
Number of
Register
Matches
single
none
none
none
any
any
Number of
Controller
Register
Matches
DRAM
single
none
none
none
any
any
on-chip SRAM
SBC 2
SBC 1
as defined by Chip-Select control register
as defined by DRAM control register
Undefined
Undefined
Type of Access
Figure
Freescale Semiconductor
8-4.
Figure 8-4