MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 589

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

24.11 Device Operational Model
The function of the device operation is to transfer a request in the memory image to and from the Universal
Serial Bus. Using a set of linked list transfer descriptors, pointed to by a queue head, the device controller
will perform the data transfers. The following sections explain the use of the device controller from the
device controller driver (DCD) point-of-view and further describe how specific USB bus events relate to
status changes in the device controller programmer's interface.
24.11.1 Device Controller Initialization
After a hardware reset, the USB OTG controller is disabled until the Run/Stop bit is set to a '1'. In the
disabled state, the pull-up on the USB D+ is not active which prevents an attach event from occurring. At
a minimum, it is necessary to have the queue heads setup for endpoint zero before the device attach occurs.
Shortly after the device is enabled, a USB reset will occur followed by setup packet arriving at endpoint
0. A Queue head must be prepared so that the device controller can store the incoming setup packet.
In order to initialize a device, the software should perform the following steps:
Freescale Semiconductor
1. Set Controller Mode to device mode. Optionally set Streaming Disable in the USBMODE register.
2. Optionally modify the BURSTSIZE register.
3. Allocate and Initialize device queue heads in system memory Minimum: Initialize device queue
4. Configure ENDPOINTLISTADDR Pointer.
5. Enable the microprocessor interrupt associated with the USB OTG and optionally change setting
0;11–0 Current Offset. Offset into the 4kb buffer where the packet is to begin.
1;10–0 Frame Number. Written by the device controller to indicate the frame number in which a packet finishes. This
31–12 Buffer Pointer. Selects the page offset in memory for the packet buffer. Non virtual memory systems will
Bit
heads 0 Tx and 0 Rx.
For information on device queue heads, refer to
For additional information on ENDPOINTLISTADDR, refer
of ITC field in USBCMD register.
typically set the buffer pointers to a series of incrementing integers.
is typically be used to correlate relative completion times of packets on an ISO endpoint.
Transitioning from host mode to device mode requires a device controller
reset before modifying USBMODE.
All device queue heads must be initialized for control endpoints before the
endpoint is enabled. Device queue heads for non-control endpoints must be
initialized before the endpoint can be used.
Table 24-79. Buffer Page Pointer List
MCF5253 Reference Manual, Rev. 1
NOTE
NOTE
Description
Section 24.10, “Device Data
Table
24-23.
Universal Serial Bus Interface
Structures.”
24-127