MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 283

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 16
Queued Serial Peripheral Interface (QSPI) Module
This chapter describes the operation of the Queued Serial Peripheral interface module of the MCF5253
and provides its memory map and register descriptions.
16.1
The QSPI module provides a serial peripheral interface with queued transfer capability. It allows users to
queue up to 16 transfers at once, eliminating CPU intervention between transfers.
16.2
The QSPI module communicates with the core using internal memory mapped registers starting at
MBAR + $400. See
QSPI module is shown in
16.2.1
The module supports 4 external CS pins which can be decoded externally to provide control for up to 15
devices. There are a total of seven signals: QSPI_Dout, QSPI_Din, QSPI_CLK, QSPI_CS [3:0].
Peripheral chip-select signals, QSPI_CS[3:0], are used to select an external device as the source or
destination for serial data transfer. Signals are asserted at a logic level corresponding to the value of the
QSPI_CS[3:0] bits in the command RAM whenever a command in the queue is executed. More than one
chip-select signal can be asserted simultaneously.
Although QSPI_CS[3:0] will function as simple chip selects in most applications, up to 15 devices can be
selected by decoding them with an external 4-to-16 decoder.
Freescale Semiconductor
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Programmable queue to support up to 16 transfers without user intervention
Supports transfer sizes of 8 to 16 bits in 1-bit increments
Four peripheral chip-select lines for control of up to 15 devices
Programmable baud rates up to 17.5Mbps at a CPU clock of 140 MHz
Programmable delays
Programmable clock phase and polarity
Supports wraparound mode for continuous transfers
Features
QSPI
Interface and Pins
Module Overview
Section 16.4, “QSPI Memory Map and Register Definitions.”
Figure
16-1.
MCF5253 Reference Manual, Rev. 1
A block diagram of the
16-1