MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 555

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

The periodic frame list is effectively the leaf level a binary tree, which is always traversed leaf to root.
Each level in the tree corresponds to a 2
bandwidth on the USB by spreading interrupt queue heads that have the same poll rate requirement across
all the available paths from the frame list. For example, system the software can schedule eight poll rate 8
queue heads and account for them once in the high-speed bus bandwidth allocation.
When an endpoint is allocated an execution footprint that spans a frame boundary, the queue head for the
endpoint must be reachable from consecutive locations in the frame list. An example would be if 8
such an endpoint. Without additional support on the interface, to get 8
software would have to link 8
same path as 4
technique.
FSTN data structures are used to preserve the integrity of the binary-tree structure and enable the use of
the spreading technique.
hardware and software operational model requirements for using FSTNs.
The following queue head fields are initialized by the system software to instruct the host controller when
to execute portions of the split-transaction protocol.
Freescale Semiconductor
•
•
SplitXState. This is a single bit residing in the Status field of a queue head
is used to track the current state of the split transaction.
Frame S-mask. This is a bit-field where the system software sets a bit corresponding to the
micro-frame (within an H-Frame) that the host controller should execute a start-split transaction.
This is always qualified by the value of the SplitXState bit in the Status field of the queue head.
For example, referring to
indicating that if the queue head is traversed by the host controller, and the SplitXState indicates
Do_Start, and the current micro-frame as indicated by FRINDEX[2:0] is 0, then execute a
start-split transaction.
Figure 24-54. General Structure of EHCI Periodic Schedule Utilizing Interrupt Spreading
Frame List
0
Periodic
. This upsets the integrity of the binary tree and disallows the use of the spreading
Section 24.8.7, “Periodic Frame Span Traversal Node (FSTN),”
1
to 8
Figure
0b
•
•
•
MCF5253 Reference Manual, Rev. 1
. It would then have to move 4
N
24-53, case one, the S-mask would have a value of 0b0000_0001
poll rate. The software can efficiently manage periodic
8
8
8
8
8
8
8
8
7
6
5
4
3
2
1
0
Level 8
8
0b
Linkage repeats every 8 for
remainder of frame list
Level 4
4
4
4
4
3
2
1
0
1
Level 2
and everything linked after into the
0b
2
2
reachable at the correct time, the
1
0
1
Level 1
0
(Root)
Universal Serial Bus Interface
(Table
• • •
24-53). This bit
defines the
0b
were
24-93