MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 305

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor
Bit
Bit
25
24
23
22
18
17
16
15
14
13
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EBU2CNEW
EBU2VALNOGOOD
EBU2SYMERR
EBU2BITERR
UCHANRCVFULL
UCHANRCVOVER
QCHANRVFULL
QCHANOVERRUN
UQCHANSYNC
UQCHANERR
Q2CHANOVERRUN
U1CHANRCVOVER
Q1CHANRCVOVER
U2CHANRCVOVER
Q1CHANRCVFULL
Interrupt Name
UQ1CHANSYNC
PDIR3 RESYNC
Interrupt Name
UQ1CHANERR
UQ2CHANERR
EBUTXEMPTY
IIS1TXEMPTY
IIS2TXEMPTY
PDIR1RESYN
PDIR2RESYN
PDIR1UNOV
PDIR2UNOV
PDIR3 FULL
PDIR2 FULL
PDIR1 FULL
AUDIOTICK
Table 17-4. InterruptEn3 InterruptClear3, InterruptStat3 Register Description
Table 17-3. Interrupt Register Description (continued)
IEC958-2 receiver new C channel received
IEC958-2 receiver validity bit not set
IEC958-2 receiver symbol error
IEC958-2 receiver parity bit error
U2 Channel receive register full
U2 Channel receive register overrun
Q2 Channel receive register full
Q2 Channel receive register overrun
U/Q2 Channel sync found
U/Q2 Channel framing error
U1Channel receive register overrun
Q1Channel receive register full
Q1Channel receive register overrun
U/Q Channel sync found
U/Q Channel framing error
Processor data in 1 under/over
Processor data in 1 resync
Processor data in 2 under/over
Processor data in 2 resync
Tick interrupt
IEC 958 receiver 2 U/Q channel error
Processor data in 3 resync
Processor data in 3 full
I
I
EBU transmit FIFO empty
Processor data in 2 full
Processor data in 1 full
2
2
S 1 transmit FIFO empty
S 2 transmit FIFO empty
MCF5253 Reference Manual, Rev. 1
Description
Description
Vector
Vector
17
16
15
15
14
14
14
7
7
7
23
18
13
18
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Audio Interface Module (AIM)
read from PDIR2
read from PDIR1
read fromPDIR3
How to Clear
write to FIFO
write to FIFO
write to FIFO
reg. IntClear
reg. IntClear
reg. IntClear
read rcv reg
reg IntClear
reg IntClear
reg IntClear
reg IntClear
reg IntClear
reg IntClear
reg IntClear
reg IntClear
How to Clear
reg. IntClear3
reg. IntClear3
reg. IntClear3
reg. IntClear3
reg. IntClear3
reg. IntClear3
reg. IntClear3
reg IntClear3
read rcv reg
read rcv reg
17-7