MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 602

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Universal Serial Bus Interface
24.11.3.6.1 Isochronous Pipe Synchronization
When it is necessary to synchronize an isochronous data pipe to the host, the (micro)frame number
(FRINDEX register) can be used as a marker. To cause a packet transfer to occur at a specific (micro)frame
number [N], the DCD should interrupt on SOF during frame N-1. When the FRINDEX=N-1, the DCD
must write the prime bit. The USB_DR will prime the isochronous endpoint in (micro)frame N-1 so that
the device controller will execute delivery during (micro)frame N.
24.11.3.6.2 Isochronous Endpoint Bus Response Matrix
24-140
•
RX Packet Retired:
— MULT counter reaches zero
— Non-MDATA Data PID is received
— Overflow Error:
— Packet received is > maximum packet length. [Buffer Error bit is set]
— Packet received exceeds total bytes allocated in dTD. [Buffer Error bit is set]
— Fulfillment Error [Transaction Error bit is set]
— # Packets Occurred > 0 AND # Packets Occurred < MULT
— CRC Error [Transaction Error bit is set]
For TX-ISO, MULT Counter can be loaded with a lesser value in the dTD
Multiplier Override field. If the Multiplier Override is zero, the MULT
Counter is initialized to the Multiplier in the QH.
For ISO, when a dTD is retired, the next dTD is primed for the next frame.
For continuous (micro)frame to (micro)frame operation the DCD should
ensure that the dTD linked-list is out ahead of the device controller by at
least two (micro)frames.
Priming an endpoint towards the end of (micro)frame N-1 will not guarantee
delivery in (micro)frame N. The delivery may actually occur in
(micro)frame N+1 if device controller does not have enough time to
complete the prime before the SOF for packet N is received.
Setup
Out
In
Table 24-87. Isochronous Endpoint Bus Response Matrix
STALL
NULL
Packet
Ignore
Stall
1
MCF5253 Reference Manual, Rev. 1
NULL Packet
Not Primed
STALL
Ignore
CAUTION
NOTE
NOTE
Transmit
Receive
Primed
STALL
Underflow
BS Error
N/A
N/A
2
Drop Packet
Overflow
N/A
N/A
Freescale Semiconductor