MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 150

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

System Integration Module (SIM)
9.3.2
The DeviceID register is a read only register that allows the software to determine what hardware it is
running on. The register contains the part number in the upper 24 bits, the mask revision number in the
lower 8 bits, and is read as 0x005251rr, where rr is the revision number.
This register allows developers the flexibility to write code to run on more than one device. The revision
number allows developers to distinguish between different mask versions that may have minor changes or
bug fixes. For example, developers may want to distribute a single code image or library for use on
different revisions of the silicon.
9.4
For legacy reasons, there are two interrupt controllers on the MCF5253. This section provides the
programming of the two interrupt controller registers and their register descriptions.
The primary interrupt controller is centralized, and services the following:
9-6
Address MBAR2 + 0xAC
Reset
Reset
Field
7–1
•
•
•
LS
V
0
W
W
R
R
Software Watchdog Timer (SWT)
Timer modules
I
2
Table 9-4. Second Module Base Address Register (MBAR2)Field Descriptions (continued)
C0 module
Interrupt Interface Registers
31
15
If interrupts in both the “primary” and the “secondary” interrupt controllers have the same interrupt level pending
then bits LS[7:1] determine which interrupt controller gets priority.
If the bit is cleared, the primary interrupt controller gets priority. If the bit is set, the secondary interrupt controller
gets priority.
There are 7 LSn bits, one for each interrupt level.
The Valid bit defines if the CPU can access the MBAR2 mapped peripherals.
0 MBAR2 address space not visible by CPU
1 MBAR2 address space visible by CPU
0
0
Device ID Register
30
14
0
1
29
13
0
0
Part Number
28
12
0
1
Figure 9-3. DeviceID Register (DeviceID)
27
11
0
0
MCF5253 Reference Manual, Rev. 1
26
10
0
0
25
0
0
9
Part Number
Description
24
0
1
8
23
0
–
7
22
1
–
6
21
0
–
5
Mask Revision
20
1
–
4
19
0
–
3
Freescale Semiconductor
18
Access: User read
0
–
2
17
1
–
1
16
0
0
0