MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 38

IC MPU 32BIT 140MHZ 225-MAPBGA

MCF5253CVM140

Manufacturer Part Number
MCF5253CVM140
Description
IC MPU 32BIT 140MHZ 225-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF525xr

Specifications of MCF5253CVM140

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
140MHz
Connectivity
CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
Peripherals
DMA, WDT
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
225-MAPBGA
Family Name
MCF5xxx
Device Core
ColdFire V2
Device Core Size
32b
Frequency (max)
140MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.2/3.3V
Operating Supply Voltage (max)
1.32/3.6V
Operating Supply Voltage (min)
1.08/3V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
225
Package Type
MA-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant

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MCF5253 Introduction
1-6
— Programmable clock phase and polarity
— Supports wraparound mode for continuous transfers
— Master mode only
Dual 16-bit General-purpose Multimode Timers
— Clock source selectable from external, CPU clock/2 and CPU clock/32.
— 8-bit programmable prescaler
— 1 output
— Processor-interrupt capability
— 14.3 nS resolution with CPU clock at 140 MHz
SmartMedia Interface
Analog/Digital Converter
— 12-Bit Resolution
— 6 Muxed inputs
Flash Memory Card Interface
— Allows connection to Sony MemoryStick compatible devices
— Support Secure Digital (SD) cards and other types of flash media (Multi-Media Card).
Dual I
— Interchip communication bus interface for EEPROMs, LCD controllers, A/D converters,
— Master and slave modes, support for multiple masters
— Automatic interrupt generation with programmable level
System debug support
— Real-time instruction trace for determining dynamic execution path
— Background debug mode (BDM) for debug features while halted
— Debug exception processing capability
— Real-time debug support
System Interface
— Glueless bus interface and DRAMC support for interfacing to 16-bit DRAM, SRAM, ROM,
— Three programmable chip-select signals for static memories or peripherals with programmable
— One dedicated chip select for 16-bit wide DRAM/SDRAM.
— The device can boot from external memory or from its own internal boot ROM. If selected to
— Programmable interrupt controller (low interrupt latency, seven external interrupt requests,
— Up to 57 programmable general-purpose outputs
— Up to 60 programmable general-purpose inputs
keypads, CD-DSP’s
FLASH, and I/O devices
wait states and port sizes.
boot from external memory (Flash / ROM) then CS0 is active after reset.
programmable autovector generator)
2
C Interfaces
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor

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