MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 568

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Universal Serial Bus Interface
There exists a one-to-one relationship between a high-speed isochronous split transaction (including all
start- and complete-splits) and one full-speed isochronous transaction. An siTD contains (amongst other
things) buffer state and split transaction scheduling information. An siTD's buffer state always maps to one
full-speed isochronous data payload. This means that for any full-speed transaction payload, a single
siTD's data buffer must be used. This rule applies to both IN an OUTs. An siTD's scheduling information
usually also maps to one high-speed isochronous split transaction. The exception to this rule is the
H-Frame boundary wrap cases mentioned above.
The siTD data structure describes at most, one frame's worth of high-speed transactions and that
description is strictly bounded within a frame boundary.
top are examples of the full-speed transaction footprints for the boundary scheduling cases described
above. In the middle are time-frame references for both the B-Frames (HS/FS/LS Bus) and the H-Frames.
On the bottom is illustrated the relationship between the scope of an siTD description and the time
references. Each H-Frame corresponds to a single location in the periodic frame list. The implication is
that each siTD is reachable from a single periodic frame list location at a time.
Each case is described as follows:
24-106
•
•
H-Frame
4
5
Case 1: One siTD is sufficient to describe and complete the isochronous split transaction because
the whole isochronous split transaction is tightly contained within a single H-Frame.
Case 2a, 2b: Although both INs and OUTs can have these footprints, OUTs always take only one
siTD to schedule. However, INs (for these boundary cases) require two siTDs to complete the
scheduling of the isochronous split transaction. siTDX is used to always issue the start-split and
the first N complete-splits. The full-speed transaction (for these cases) can deliver data on the
full-speed bus segment during micro-frame 7 of H-Frame
The complete splits are scheduled using siTD
data must use the buffer pointer from siTD
siTD
B-Frame
5
6
Y–1
X+1
6
7
Y–1
from H-Frame
7
0
0
1
Case 1
1
2
Figure 24-58. siTD Scheduling Boundary Examples
H-Frame
2
Y+2
3
siTD
B-Frame
4
3
is to use siTD
X
MCF5253 Reference Manual, Rev. 1
Y
4
5
Full-Speed Transaction
Y
Case 2a
5
6
Back Pointer
6
7
X+2
X+1
7
0
's back pointer.
X+2
. The only way for the host controller to reach
0
1
Figure 24-58
(not shown). The complete-splits to extract this
1
2
H-Frame
2
siTD
3
Y+1
B-Frame
Case 2b
4
X+1
3
, or micro-frame 0 of H-Frame
Y+1
illustrates some examples. On the
4
5
Y+1
5
6
6
7
7
0
Freescale Semiconductor
H-Frame
0
1
B-Frame
1
2
Y+2
2
3
Y+2
Y+2
.