MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 327

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

17.7.2.1
The DataInControl register determines what data will be in the PDIR1 input FIFO, in PDIR2 input FIFO,
and in the PDIR3 input FIFO. All FIFO’s are six-deep, and have programmable “full” indication.
Address MBAR2 + 0x30 (Reset 0x00)
Freescale Semiconductor
Reset
Reset
•
•
W
W
R
R
PDIR3 RESET
PDIR3 ZERO
Data flowing in is selected by source multiplexer 16a. Control via register DataInControl (12, 2:0).
Table
PDIR2 (Processor data in). Same function as PDIR1. Single 32-bit register contains both Left +
Right in 16-bit precision. Data flowing in is selected by source multiplexer 16. Control via register
DataInControl(13,5:3)
PDIR3-L, PDIR3-R (Processor data in). This function is identical to PDIR1. Data flowing in is
selected by source multiplexer 16b. Control via register DataInControl(19:16).
PDIR2 FULL
INTERRUPT
CONTROL
31
15
SELECT
0
0
31–24
Field
23
22
Data In Selection
17-15.
30
14
0
0
The DataInControl register bits 7:6 allow selection when FIFO full flag is
set. This is necessary due to polling. It may be necessary to service the FIFO
when it is less than completely full. For PDIR2 only, interrupt-driven and
DMA-driven read-out is supported.
SELECT
PDIR2
29
13
0
0
Reserved.
0 Normal operation
1 Always read zero from PDIR3
0 Normal operation
1 Reset PDIR3 to one sample remaining
Table 17-15. DataInControl Register Field Descriptions
SELECT
PDIR1
28
12
0
0
Table
PDIR2
ZERO
CTRL
Figure 17-16. DataInControl Register
27
11
0
0
MCF5253 Reference Manual, Rev. 1
17-15.
PDIR1
ZERO
CTRL
26
10
0
0
RESET
PDIR2
25
0
0
9
NOTE
Description
RESET
PDIR1
24
0
0
8
PDIR3
ZERO
CTRL
PDIR1 FULL
INTERRUPT
23
0
0
7
SELECT
RESET
PDIR3
22
0
6
0
INTERRUPT
PDIR3 FULL
SELECT PDIR2
21
0
0
5
Audio Interface Module (AIM)
20
0
0
4
Access: User read/write
Table
19
0
3
0
SELECT PDIR3
SELECT PDIR1
18
17-15.
0
0
2
Reset
0
0
0
17
0
0
1
17-29
16
0
0
0