MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 513

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

24.8.3.3
DWords 9
buffer for this transfer descriptor. This data structure requires the associated data buffer to be contiguous
(relative to virtual memory), but allows the physical memory pages to be non-contiguous. Seven page
pointers are provided to support the expression of eight isochronous transfers. The seven pointers allow
for 3 (transactions) × 1024 (maximum packet size) × 8 (transaction records) = 24576 bytes to be moved
with this data structure, regardless of the alignment offset of the first page.
Since each pointer is a 4K aligned page pointer, the least significant 12 bits in several of the page pointers
are used for other purposes.
Freescale Semiconductor
14–12
31–12 Buffer Pointer
31–12
11–0
10–0
11–8
Bit
Bit
Bit
6–0
11
7
Transaction n
Device Address This field selects the specific device serving as the data source or sink.
Packet Size
Buffer Pointer
Maximum
–
(Page 1)
15 of an isochronous transaction descriptor are nominally page pointers (4K aligned) to the data
Name
Offset
Name
(Page 0)
PG
I/O
Name
EndPt
iTD Buffer Page Pointer List (Plus)
–
These bits are set by the software to indicate which of the buffer page pointers the offset field in this
slot should be concatenated to produce the starting memory address for this transaction. The valid
range of values for this field is 0 to 6.
This field is a value that is an offset, expressed in bytes, from the beginning of a buffer. This field is
concatenated onto the buffer page pointer indicated in the adjacent PG field to produce the starting
buffer address for this transaction.
This is a 4K aligned pointer to physical memory. Corresponds to memory address bits [31–12].
Direction (I/O). This field encodes whether the high-speed transaction should use an IN or OUT PID.
0 Out
1 In
This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize).
This field is used for high-bandwidth endpoints where more than one transaction is issued per
transaction description (.for example, per micro-frame). This field is used with the Multi field to support
high-bandwidth pipes. This field is also used for all IN transfers to detect packet babble. The software
should not set a value larger than 1024 (400h). Any value larger yields undefined results.
Table 24-39. iTD Transaction Status and Control (continued)
This is a 4K aligned pointer to physical memory. Corresponds to memory address bits [31–12].
This 4-bit field selects the particular endpoint number on the device serving as the data source or
sink.
Reserved. Reserved for future use and should be initialized by he software to zero.
Table 24-41. iTD Buffer Pointer Page 1 (Plus)
Table 24-40. Buffer Pointer Page 0 (Plus)
MCF5253 Reference Manual, Rev. 1
Description
Description
Description
Universal Serial Bus Interface
24-51