MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 457

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

23.5.2.5.3
See
description of the bit fields.
23.5.2.6
See
Freescale Semiconductor
Address MBAR2 + 0x830 (INTERRUPT_CLEAR)
fifo_underflow
Uncommitted
Uncommitted
Uncommitted
fifo_overflow
ata_intrq2
Reset
Field
Field
Figure 23-42
Figure 23-43
2–0
4–0
3
W
7
6
5
R
7
–
ATA interrupt request 2. This bit reflects the value of the ATA_INTRQ interrupt input. It is set in the interrupt
pending register when the drive interrupt is pending, cleared otherwise. It has exactly same functioning as
ata_intrq1, but this bit affects ipbus_int, while the other affects interrupt to the DMA. When the bit is set in the
interrupt pending register, and the same bit is set in the interrupt enable register, ipbus_int will be asserted,
signalling the CPU the drive is requesting attention. The interrupt clear register has no influence on this bit.
N/A
N/A
FIFO underfow. This bit reports FIFO underflow. Sticky bit. It is set in the interrupt pending register when there
is a FIFO underflow condition. It is cleared by writing a ‘1’ to this bit in the interrupt clear register. When the bit
is set in the interrupt pending register, and the same bit is set in the interrupt enable register, ipbus_int will be
active, signalling interrupt to the cpu.
FIFO overflow. This bit reports FIFO overflow. Sticky bit. It is set in the interrupt pending register when there is
a FIFO overflow condition. It is cleared by writing a ‘1’ to this bit in the interrupt clear register. When the bit is set
in the interrupt pending register, and the same bit is set in the interrupt enable register, ipbus_int will be active,
signalling interrupt to the cpu.
N/A
FIFO Alarm Register
Interrupt_Clear Register
for illustration of valid bits in the Interrupt_Clear Register and
for illustration of valid bits in the FIFO_Alarm Register.
Table 23-12. Interrupt Enable Register Field Description (continued)
fifo_underflow
Table 23-13. Interrupt Clear Register Field Description
6
–
Figure 23-42. Interrupt_Clear Register
fifo_overflow
MCF5253 Reference Manual, Rev. 1
5
–
4
–
Description
Description
–
3
Advanced Technology Attachment Controller (ATA)
–
2
Table 23-13
Access: User write-only
–
1
for
–
0
23-31