MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 551

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

24.9.12 Split Transactions
USB 2.0 defines extensions to the bus protocol for managing USB 1.x data streams through USB 2.0 hubs.
This section describes how the host controller uses the interface data structures to manage data streams
with full- and low-speed devices, connected below a USB 2.0 hub, utilizing the split transaction protocol.
Refer to the USB 2.0 Specification for the complete definition of the split transaction protocol. Full- and
low-speed devices are enumerated identically as high-speed devices, but the transactions to the full- and
low-speed endpoints use the split-transaction protocol on the high-speed bus. The split transaction protocol
is an encapsulation of (or wrapper around) the full- or low-speed transaction. The high-speed wrapper
portion of the protocol is addressed to the USB 2.0 hub and Transaction Translator below which the full-
or low-speed device is attached.
EHCI uses dedicated data structures for managing full-speed isochronous data streams. Control, Bulk and
Interrupt are managed using the queuing data structures. The interface data structures need to be
programmed with the device address and the Transaction Translator number of the USB 2.0 hub operating
as the low-/full-speed host controller for this link. The following sections describe the details of how the
host controller processes and manages the split transaction protocol.
24.9.12.1 Split Transactions for Asynchronous Transfers
A queue head in the asynchronous schedule with an EPS field indicating a full-or low-speed device
indicates to the host controller that it must use split transactions to stream data for this queue head. All
full-speed bulk and full-, low-speed control are managed via queue heads in the asynchronous schedule.
The software must initialize the queue head with the appropriate device address and port number for the
transaction translator that is serving as the full-/low-speed host controller for the links connecting the
endpoint. The software must also initialize the split transaction state bit (SplitXState) to Do-Start-Split.
Finally, if the endpoint is a control endpoint, then system The software must set the Control Transfer Type
(C) bit in the queue head to a one. If this is not a control transfer type endpoint, the C bit must be initialized
by the software to be a zero. This information is used by the host controller to properly set the Endpoint
Type (ET) field in the split transaction bus token. When the C bit is a zero, the split transaction token's ET
field is set to indicate a bulk endpoint. When the C bit is a one, the split transaction token's ET field is set
to indicate a control endpoint. Refer to Chapter 8 of USB Specification, Revision 2.0 for details.
Freescale Semiconductor
Error Count
Decrement
Figure 24-52. Host Controller Asynchronous Schedule Split-Transaction State Machine
Endpoint Halt
(CERR)
CERR goes
to Zero
XactErr
Endpoint Active
NaK
MCF5253 Reference Manual, Rev. 1
Start-
Split
Do
!XactErr
!NYET
.and.
.and.
!Stall
AcK
Complete-
Split
Do
Nyet
PidCode .eq. SETUP
XactErr
Endpoint Halt
Decrement Error Count
.and.
NaK
Set XactErr Bit and
Stall
(CERR)
Do Immediate Retry
of Complete-Split
Universal Serial Bus Interface
Error Count
Decrement
CERR goes
(CERR)
to Zero
and
24-89