MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 263

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

15.4.3
The USR registers indicate the status of the characters in the receive FIFO and the status of the transmitter
and receiver. The RB, FE, and PE bits are cleared by the Reset Error Status command in the UCR registers
if the RB bit has not been read. Also, RB, FE, PE and OE can also be cleared by reading the Receive buffer
(URB).
Freescale Semiconductor
TxCTS
TxRTS
Field
7–6
3–0
CM
SB
5
4
Channel mode.
Selects a channel mode.
00 Normal
01 Automatic echo
10 Local loop-back
11 Remote loop-back
Transmitter ready-to-send.
Controls negation of RTS to automatically terminate a message transmission when the transmitter is disabled after
completion of a transmission. Attempting to program a receiver and transmitter in the same channel for RTS control
is not permitted and disables RTS control for both.
0 The transmitter has no effect on RTS.
1 When the transmitter is disabled after transmission completes, setting this bit automatically clears UOP[RTS] one
Note: Not available on UART2.
Transmitter clear-to-send.
If both TxCTS and TxRTS are enabled, TxCTS controls the operation of the transmitter.
0 CTS has no effect on the transmitter.
1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character.
Note: Not available on UART2
Stop-bit length control.
Selects the length of the stop bit appended to the transmitted character. Stop-bit lengths of 9/16th to 2 bits are
programmable for 6–8 bit characters. Lengths of 1 1/16th to 2 bits are programmable for 5-bit characters. In all cases,
the receiver checks only for a high condition at the center of the first stop-bit position, that is, one bit time after the
last data bit or after the parity bit, if parity is enabled. If an external 1x clock is used for the transmitter, clearing bit 3
selects one stop bit and setting bit 3 selects 2 stop bits for transmission.
bit time after any characters in the channel transmitter shift and holding registers are completely sent, including
the programmed number of stop bits.
If CTS is asserted, the character is sent; if it is negated, the channel TxD remains in the high state and
transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its
transmission.
Status Registers (USRn)
Table 15-6. Mode Register 2 (UMR2n) Field Descriptions
Section 15.3.3, “Looping
0000
0001
0010
0011
0100
0101
0110
0111
SB
MCF5253 Reference Manual, Rev. 1
5 Bits
1.063
1.125
1.188
1.250
1.313
1.375
1.438
1.500
6–8 Bits
0.563
0.625
0.688
0.750
0.813
0.875
0.938
1.000
Modes,”
Description
describes individual modes.
1000
1001
1010
1011
1100
1101
1110
1111
SB
5 Bits
1.563
1.625
1.688
1.750
1.813
1.875
1.938
2.000
6–8 Bits
1.563
1.625
1.688
1.750
1.813
1.875
1.938
2.000
UART Modules
15-17