MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 527

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

The DWords 4–11 of a queue head are the transaction overlay area. This area has the same base structure
as a Queue Element Transfer Descriptor. The queue head utilizes the reserved fields of the page pointers
to implement tracking the state of split transactions.
This area is characterized as an overlay because when the queue is advanced to the next queue element,
the source queue element is merged onto this area. This area serves an execution cache for the transfer.
24.8.7
This data structure is to be used only for managing Full- and Low-speed transactions that span a
Host-frame boundary. The software must not use an FSTN in the Asynchronous Schedule. An FSTN in
the Asynchronous schedule results in undefined behavior. The software must not use the FSTN feature
with a host controller whose HCIVERSION register indicates a revision implementation below 0x0096.
Note that FSTNs were not defined for EHCI implementations before Revision 0.96 of the EHCI
Specification and their use may yield undefined results.
Freescale Semiconductor
31
DWord QH Offset
5
6
6
6
6
8
9
9
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0x14
0x18
0x18
0x18
0x18
0x20
0x24
0x24
Periodic Frame Span Traversal Node (FSTN)
Table 24-59. Host-Controller Rules for Bits in Overlay (DWords 5, 6, 8 and 9)
11–1
11–5
4–1
7–0
4–0
Bit
31
15
0
0
C-prog-mas
FrameTag
Status[0]
Figure 24-42. Frame Span Traversal Node Structure
NakCnt
S-bytes
Name
Cerr
ioc
dt
k
Normal Path Link Pointer
Back Path Link Pointer
MCF5253 Reference Manual, Rev. 1
Nak counter—RW. This field is a counter the host controller decrements
whenever a transaction for the endpoint associated with this queue head results
in a Nak or Nyet response. This counter is reloaded from RL before a transaction
is executed during the first pass of the reclamation list (relative to an
Asynchronous List Restart condition). It is also loaded from RL during an overlay.
Data toggle. The Data Toggle Control controls whether the host controller
preserves this bit when an overlay operation is performed.
Interrupt on complete. The ioc control bit is always inherited from the source qTD
when the overlay operation is performed.
Error counter. This two-bit field is copied from the qTD during the overlay and
written back during queue advancement.
Ping state (P)/ERR. If the EPS field indicates a high-speed endpoint, then this
field should be preserved during the overlay operation.
Split-transaction complete-split progress. This field is initialized to zero during any
overlay. This field is used to track the progress of an interrupt split-transaction.
The software must ensure that the S-bytes field in a qTD is zero before activating
the qTD. This field is used to keep track of the number of bytes sent or received
during an IN or OUT split transaction.
Split-transaction frame tag. This field is initialized to zero during any overlay. This
field is used to track the progress of an interrupt split-transaction.
15
14 13 12 11 10
Description
9
8
7
6
Universal Serial Bus Interface
5
4
00
00
3
2
Typ
Typ
1
T 0x00
T 0x04
0
Offset
24-65