MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 68

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

ColdFire Core
3.2.3.2
The VBR contains the base address of the exception vector table in memory. The displacement of an
exception vector is added to the value in this register to access the vector table. The lower 20 bits of the
VBR are not implemented by ColdFire processors; they are zero, forcing the table to be aligned on a
1-megabyte boundary.
3.3
Exception processing for ColdFire processors is streamlined for performance. The ColdFire processors
provide a simplified exception processing model. The next section details the model.Differences from
previous 68000 Family processors include:
ColdFire processors use an instruction restart exception model but do require more software support to
recover from certain access errors. Refer to
Exception processing is comprised of four major steps and is defined as the time from the detection of the
fault condition to the fetch of the first handler instruction has been initiated.
3-6
I [2–0]
Field
•
•
•
•
1. The processor makes an internal copy of the SR and then enters supervisor mode by setting the S
M
T
S
A simplified exception vector table
Reduced relocation capabilities using the vector base register
A single exception stack frame format
Use of a single self-aligning system stack
bit and disabling trace mode by clearing the T bit. The occurrence of an interrupt exception also
forces the M bit to be cleared and the interrupt priority mask to be set to the level of the current
interrupt request.
Rc [11–0]
Exception Processing Overview
When set, the trace enable allows the processor to perform a trace exception after every instruction.
The supervisor / user state bit denotes whether the processor is in supervisor mode (S=1) or user mode (S=0).
The master / interrupt state bit is cleared by an interrupt exception, and can be set by software during execution of
the RTE or move to SR instructions.
The interrupt priority mask defines the current interrupt priority. Interrupt requests are inhibited for all priority levels
less than or equal to the current priority, except the edge-sensitive level 7 request, which cannot be masked.
Reset
Field
R/W Written from a BDM serial command or from the CPU using the MOVEC instruction. VBR can be read
Vector Base Register (VBR)
from the debug module only. The upper 12 bits are returned, the low-order 20 bits are undefined.
Exception vector table base address
Table 3-4. Status Register Field Descriptions
Figure 3-5. Vector Base Register (VBR)
MCF5253 Reference Manual, Rev. 1
30 –21
0000_0000_0000_0000_0000_0000_0000_0000
Section 3.5.1, “Access Error Exception,”
Description
0x801
19 –0
Freescale Semiconductor
–
for details.