MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 184

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Chip Select Module
10.4.2.3
CSCRx control the auto acknowledge, external master support, port size, burst capability, and activation
of each of the chip selects.
For CSCR0, bits BSTR, and BSTW are initialized to 0 by reset; bits WS[3:0] and BEM are initialized to
1 by reset; while AA, PS1, and PS0 are loaded with “110”, respectively at reset. For CSCR1 to CSCR4
none of the bits are initialized at reset. These are shown in
CS0 is the global (boot) chip select which allows address decoding for boot ROM before system
initialization occurs. Its operation differs from the other external chip select outputs following a system
reset.
10-8
Address MBAR + 0x8A (CSCR0)
Reset
AM, C/I, SC,
SD, UC, UD
W
Field
R
6–1
V
0
15
–
Chip Select Control Register
Table 10-4. Chip Select Mask Register (CSMRx) Field Descriptions (continued)
These fields mask specific address spaces.
If an address space mask bit were cleared, an access to a location in that address space can activate the
corresponding chip select. If an address space mask bit were set, an access to a location in that address
space becomes a regular external bus access, and no chip select is activated.
AM: Alternate master access (DMA)
C/I: Interrupt cycle access
SC: Supervisor code access
SD: Supervisor data access
UC: User code access
UD: User data access
For each address space mask bit (AM, C/I, SC, SD, UC, UD):
0 Do not mask this address space for the chip select. An access using the chip select can occur for this
1 Mask this address space from the chip select activation. If this address space is accessed, no chip select
The Valid bit indicates that the contents of its address register, mask register, and control register are valid.
The programmed chip selects do not assert until the V-bit is set (except for CS0 which acts as the global
(boot) chip select—see
A reset clears the V-bit in each CSMR.
0 Chip select invalid
1 Chip select valid
14
–
address space.
activation occurs on the external cycle.
WS3 WS2 WS1 WS0
13
1
12
Figure 10-3. Chip Select Control Register (CSCR0)
1
11
1
Section 10.3.3, “Global Chip-Select
MCF5253 Reference Manual, Rev. 1
10
1
–
9
AA
1
8
Description
PS1
1
7
Figure 10-3
PS0
0
6
Operation.”)
–
5
and
BSTR
Figure
0
4
BSTW
10-4.
Freescale Semiconductor
0
3
Access: User read/write
–
2
–
1
0
0