MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 383

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

debug module initiates a memory read operation. Any serial transfers that begin while the memory access
is in progress return the “not ready” response.
Results are returned in the two serial transfer cycles following the completion of the memory access. The
data transmitted to the debug module during the final transfer is the opcode for the following command.
If a memory or register access is terminated with a bus error, the error status (S=1, DATA=$0001) is
returned in place of the result data.
20.3.4.1
The BDM command set is summarized in
of each command.
Unassigned command opcodes are reserved by Freescale for future expansion. All unused command
formats within any revision level perform a NOP and return the ILLEGAL command response.
20.3.4.1.1
RAREG and RDREG reads the selected address or data register and return the 32-bit result. A bus error
response is returned if the CPU core is not halted.
Command Sequence:
Operand Data:
None
Freescale Semiconductor
Command Set Descriptions
The BDM status bit (S) is zero for normally-completed commands, while
illegal commands, “not ready” responses and bus-error transfers return a
logic one in the S bit. Refer to
information on the serial packet receive packet format.
Read Address/Data Register (RAREG/RDREG)
RAREG/RDREG
Figure 20-9. Read A/D Register Command Sequence
???
Figure 20-8. Command/Result Formats
MCF5253 Reference Manual, Rev. 1
Table
Section 20.3.2, “BDM Serial Interface,”
20-5. Subsequent sections contain detailed descriptions
NOTE
MS Result
BERR
XXX
XXX
“Not Ready”
Next CMD
Next CMD
LS Result
Background Debug Mode (BDM) Interface
for
20-13