MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 331

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Address MBAR2 + 0xCC
The controller will stay in the Off state when the feature is disabled. When not disabled, the state machine
will go to the Off state on any processor read or write to the FIFO. It will go from On or Off to Standby on
any left sample read from IIS, IIS2, and EBU Tx FIFO’s, or on any left sample write to PDIR1, PDIR2,
PDIR3 FIFO’s. The controller will go from Standby to On on any right sample read from IIS1, IIS2 and
EBU Tx FIFO’s, or on any right sample write to PDIR1, PDIR2 and PDIR3.
17.7.6
Figure 17-18
of the bit fields.
Freescale Semiconductor
Reset
Field
12
10
9
8
7
W
R
Off
15
0
PDIR3 FIFO AUTO SYNC
EBU TX AUTO SYNC
IIS2 FIFO AUTO SYNC
IIS1 FIFO AUTO SYNC
PDIR2 FIFO AUTO SYNC
audioGlob Register Descriptions
14
0
illustrates the valid bits in the audioGlob Register and
Read left sample from IIS1, IIS2, EBU
Write left sample to PDIR1, PDIR2
13
0
Figure 17-17. Automatic Resynchronization FSM of Left-Right FIFOs
Processor write to IIS1, IIS2, EBU fifo
Processo read from PDIR1, PDIR2
PDIR3
AUTO
SYNC
FIFO
Name
12
0
Table 17-19. audioGlob Register Field (0xCE) Descriptions
AUDIOTICK
EBU2 EXT
SOURCE
11
0
Figure 17-18. audioGlob Register
MCF5253 Reference Manual, Rev. 1
EBU1 TX
0 Auto synchronization off
1 Auto synchronization on
1 Auto synchronization on
0 Auto synchronization off
1 Auto synchronization on
0 Auto synchronization off
1 Auto synchronization on
0 Auto synchronization off
1 Auto synchronization on
0 Auto synchronization off
AUTO
SYNC
10
0
Standby
FIFO
IIS2
0
9
Read right sample from IIS1, IIS2, EBU
Write right sample to PDIR1, PDIR2
Description
AUTO
SYNC
0
8
Read left sample from IIS1, IIS2, EBU
Write left sample to PDIR1, PDIR2
PDIR2
AUTO
SYNC
FIFO
1
0
7
Table 17-19
PDIR1
AUTO
SYNC
FIFO
0
6
provides the description
Audio Interface Module (AIM)
AUDIO_TICK
0
5
Reset
COUNT
0
0
0
0
0
Access: User read/write
0
4
0
3
On
0
2
AUDIOTICK
Notes
SOURCE
1
0
17-33
0
0