MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 373

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

20.1.7
Since the debug trace port signals transition each processor cycle and are not related to the external bus
frequency, an additional signal is output from the ColdFire microprocessor. The PSTCLK signal is a
delayed version of the processor’s high-speed clock and its rising-edge is used by the development system
to sample the values on the PST and DDATA output buses. The PSTCLK signal is intended for use in the
standard 26-pin debug connector. See
If the real-time trace functionality is not being used, the PCD bit of the CSR may be set (CSR[17] = 1) to
force the PSTCLK, PST, and DDATA outputs to be disabled.
20.2
In the area of debug functions, one fundamental requirement is support for real-time trace functionality.
For example, definition of the dynamic execution path. The ColdFire solution is to include a parallel output
port providing encoded processor status and data to an external development system. This port is
partitioned into two nibbles (4 bits): one nibble allows the processor to transmit information concerning
the execution status of the core (processor status: PST), while the other nibble allows operand data to be
Freescale Semiconductor
Real-Time Trace Support
Note: †These encodings are asserted for multiple cycles.
Processor Status Clock (PSTCLK)
(Hex)
$C
$D
$A
$B
$E
$F
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
PST[3:0]
Table 20-1. Processor Status Encoding
MCF5253 Reference Manual, Rev. 1
Figure
(Binary)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
20-39.
Continue execution
Begin execution of an instruction
Reserved
Entry into user-mode
Begin execution of PULSE and WDDATA
instructions
Begin execution of taken branch or Sync_PC
Reserved
Begin execution of RTE instruction
Begin 1-byte transfer on DDATA
Begin 2-byte transfer on DDATA
Begin 3-byte transfer on DDATA
Begin 4-byte transfer on DDATA
Exception processing†
Emulator-mode entry exception processing†
Processor is stopped, waiting for interrupt†
Processor is halted †
Definition
Background Debug Mode (BDM) Interface
20-3