MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 330

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Audio Interface Module (AIM)
1
2
3
4
17.7.4
All PDOR and PDIR registers have different FIFOs for left and right channels. As a result, there is always
the possibility that the left and right FIFOs may go out of sync due to FIFO underruns and FIFO overruns
that affect only one part (left or right) of any FIFO. To prevent this from happening, two hardware
mechanisms are available:
17.7.5
An automatic FIFO resynchronization feature is available on the MCF5253. It can be enabled or disabled
separately for every FIFO. If enabled, the hardware will check if the left and right FIFOs are in sync, and
if not, it will set the filling pointer of the right FIFO to be equal to the filling pointer of the left FIFO.
The operation is shown in
states:
In the On state, the filling of the left FIFO is compared with the filling of right, and if they are not equal,
right is made equal to left, and an interrupt is generated.
17-32
L18 is bit 18 of left sample, ~L19 is inverse of bit 19 of left sample, R18 is bit 18 of right sample.
If incoming/outgoing interface use 16, 18 bits, data is aligned at the MSB side. LSB ‘s D1-D0 or D3-D0 will read all-zero. Written
values are disregarded.
PDOR3, PDIR2 use only 16 MSB of both left and right.
Inversion of MSB ‘s L19 and R19 translates the format from 2-complement to unsigned.
(The continuous range e.g. -0x8000 to +7FFF is translated to 0 to +0xFFFF)
1. If PDIR1, PDIR2, or PDIR3 FIFO overrun occurs on, as an example, the right half of the FIFO, the
2. If IIS1 or IIS2 Tx FIFO, or EBU Tx FIFO underruns on, for example, the right half of the FIFO,
1. Off
2. Stand-By
3. On
sample that caused the overrun is not written to the right half (due to overrun). Special hardware
will make sure the next sample is not written to the left half of the FIFO. If the overrun occurs on
the left half of the FIFO, the next sample is not written to the right half of the FIFO.
no sample leaves that FIFO. (because it was already empty.) Special hardware ensures that the next
sample read from the left FIFO will not leave the FIFO. (No read strobe is generated). If the
underrun occurs on the left half of the FIFO, next read strobe to the right FIFO is blocked.
Overrun and Underrun with PDIR and PDOR Registers
Automatic Resynchronization of FIFOs
Figure
17-17. Every FIFO auto-resync controller has a state machine with three
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor