MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 231

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

14.3
The DMA controller module usually transfers data at rates much faster than the ColdFire core under
software control can handle. The term DMA refers to the ability for a peripheral device to access memory
in a system in the same manner as the core. DMA operations can greatly increase overall system
performance.
The DMA module consists of four independent channels. The term DMA is used throughout this section
to reference any of the four channels, as they are all functionally equivalent. It is impossible to implicitly
address all four DMA channels at the same time.
DMA requests can be generated by the processor writing to the START bit in the DMA control register or
generated by an on-chip peripheral device asserting one of the REQUEST signals. The processor can
program the amount of bus bandwidth allocated for the DMA for each channel. The DMA channels
support continuous and cycle-steal transfer modes.
The DMA controller supports dual-address transfers. In dual-address mode, the DMA channel supports 32
bits of address and 32 bits of data. Dual-address transfers can be initiated by either a processor request
using the START bit or by an internal peripheral device using the REQUEST signal. Two bus transfers
occur in this mode, a read from a source device and a write to a destination device (see
Any operation involving the DMA module follows the same three basic steps:
Freescale Semiconductor
1. Channel initialization step—The DMA channel registers are loaded with control information,
2. Data transfer step—The DMA accepts requests for operand transfers and provides addressing and
3. Channel termination step—This occurs after operation is complete. The channel indicates the
address pointers, and a byte transfer count. Also, the DMAROUTE register is programmed to
control the source of the internal requests.
bus control for the transfers.
status of the operation in the channel status register.
DMA Module Overview
DMA
Figure 14-2. Dual Address Transfer
MCF5253 Reference Manual, Rev. 1
PERIPHERAL
PERIPHERAL
MEMORY-
MEMORY-
MEMORY
MEMORY
MAPPED
MAPPED
or
or
Figure
DMA Controller
14-2).
14-3