MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 577

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

is met the host controller immediately executes a start-split transaction and appropriately advances the
transaction state of siTD
not met, the host controller simply follows siTD
case of a 2b boundary case, the split-transaction of siTD
controller returns to the context of siTD
C-mask bits 0 and 1 set and an S-mask with bit 0 set. This scheduling combination is not supported and
the behavior of the host controller is undefined.
24.9.12.3.7 Split Transaction for Isochronous—Processing Examples
There is an important difference between how the hardware/software manages the isochronous split
transaction state machine and how it manages the asynchronous and interrupt split transaction state
machines. The asynchronous and interrupt split transaction state machines are encapsulated within a single
queue head. The progress of the data stream depends on the progress of each split transaction. In some
respects, the split-transaction state machine is sequenced using the Execute Transaction queue head
traversal state machine.
Isochronous is a pure time-oriented transaction/data stream. The interface data structures are optimized to
efficiently describe transactions that need to occur at specific times. The isochronous split-transaction state
machine must be managed across these time-oriented data structures. This means that the system software
must correctly describe the scheduling of split-transactions across more than one data structure.
Then the host controller must make the appropriate state transitions at the appropriate times, in the correct
data structures.
For example,
full-speed isochronous data stream.
This example shows the first three siTDs for the transaction stream. Since this is the case-2a frame-wrap
case, S-masks of all siTDs for this endpoint have a value of 0x10 (a one bit in micro-frame 4) and C-mask
value of 0xC3 (one-bits in micro-frames 0,1, 6 and 7). Additionally, the software ensures that the Back
Freescale Semiconductor
siTDX
X+1
X+3
X+2
X
#
Table 24-71
Table 24-71. Example Case 2a—Software Scheduling siTDs for an IN Endpoint
S-Mask
C-Mask
S-Mask
C-Mask
S-Mask
C-Mask
S-Mask
C-Mask
Masks
X
, then follows siTD
illustrates a few frames worth of scheduling required to schedule a case 2a
0
1
1
1
1
1
1
1
MCF5253 Reference Manual, Rev. 1
X
Repeats previous pattern
. Also, note that the software should not initialize an siTD with
2
X
Micro-Frames
[Next Pointer] to the next schedule item. If the criterion is
X
3
[Next Pointer] to the next schedule item. Note that in the
4
1
1
1
X-1
will have its Active bit cleared when the host
5
6
1
1
1
7
1
1
1
Do Start Split
Do Complete Split
Do Complete Split
Do Complete Split
InitialSplitXState
Universal Serial Bus Interface
24-115