MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 271

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

15.4.10
The UISR registers provides status for all potential interrupt sources. The UART Interrupt Mask Register
(UIMR) masks the contents of this register. If a flag in the UISR is set and the corresponding bit in UIMR
is also set, the internal interrupt output is asserted. If the corresponding bit in the UIMR is cleared, the state
of the bit in the UISR has no effect on the interrupt output.
Freescale Semiconductor
.
Address MBAR + $1D0 (UACR0)
Address MBAR + $1D4 (UISR0)
Field
7–1
IEC
0
Reset
Reset
W
W
R
R
Reserved
1 UISR bit 7 is set and generates an interrupt when the COS bit in the UART Input Port Change Register (UIPCR)
0 Setting the corresponding bit in the UIPCR has no effect on UISR bit 7.
MBAR + $214 (UISR1)
MBAR2 + $C14 (UISR2)
MBAR + $210 (UACR1)
MBAR2 + $C10 (UACR2)
Input Enable Control
is set by an external transition on the CTS input (if bit 7 of the interrupt mask register (UIMR) is set to enable
interrupts).
Interrupt Status Registers (UISRn)
COS
The UIMR does not mask reading of the UISR. True status is provided
regardless of the contents of UIMR. A UART module reset clears the
contents of UISR.
0
0
7
7
Table 15-15. Auxiliary Control Register (UACRn) Field Descriptions
0
0
6
6
Figure 15-16. Auxiliary Control Register (UACRn)
Figure 15-17. Interrupt Status Register (UISRn)
MCF5253 Reference Manual, Rev. 1
0
0
5
5
NOTE
0
0
4
4
Description
3
0
3
0
DB
0
2
2
0
RXRDY
Access: User write only
Access: User read only
0
0
1
1
UART Modules
TXRDY
IEC
0
0
0
0
15-25