MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 458

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Advanced Technology Attachment Controller (ATA)
Address MBAR2 + 0x834 (FIFO_ALARM)
This register contains the threshold to generate fifo_rcv_alarm and fifo_tx_alarm to the DMA interface.
23.5.2.7
Some registers are addressable, but are not present in the ATA interface module. A list is given in
Table
read or write cycle on the ATA bus, and the corresponding register in the device attached to the ATA bus
is accessed.
If the drive_data register is accessed while the ATA interface operates in big endian mode, the bytes
to/from the ATA bus are swapped. No swaps occur in little endian mode, nor for any other register.
23.6
The ATA interface provides two ways to communicate with the ATA peripherals connected to the ATA bus.
23-32
MBAR2 + 0x8A0 (DRIVE_DATA)
MBAR2 + 0x8A4 (DRIVE_FEATURES)
MBAR2 + 0x8A8 (DRIVE_SECTOR_COUNT)
MBAR2 + 0x8AC (DRIVE_SECTOR_NUM)
MBAR2 + 0x8B0 (DRIVE_CYL_LOW)
MBAR2 + 0x8B4 (DRIVE_CYL_HIGH)
MBAR2 + 0x8B8 (DRIVE_DEV_HEAD)
MBAR2 + 0x8BC (DRIVE_COMMAND)
MBAR2 + 0x8BC (DRIVE_STATUS)
MBAR2 + 0x8D8 (DRIVE_ALT_STATUS)
MBAR2 + 0x8D8 (DRIVE_CONTROL)
Reset
•
•
W
R
23-14. If a read or write access is made to one of these registers, the read or write is mapped to a PIO
If (fifo_tx_enable == 1 && fifo_fill < fifo_alarm): fifo_tx_alarm is set 1, request is made to DMA
to refill fifo.
If (fifo_rcv_alarm == 1 && fifo_fill >= fifo_alarm): fifo_rcv_alarm is set 1, request is made to
DMA to empty fifo.
Functional Description
7
0
Drive Registers Connected to ATA Bus
Address
0
6
Table 23-14. Drive Registers Connected to ATA Bus
Figure 23-43. FIFO_Alarm Register
MCF5253 Reference Manual, Rev. 1
0
5
drive_sector_count
drive_sector_num
drive_dev_head
drive_command
drive_alt_status
drive_features
drive_cyl_high
FIFO_ALARM[7:0]
drive_cyl_low
drive_control
drive_status
0
4
drive_data
Name
0
3
Drive data register
Drive features register
Drive sector count register
Drive sector number register
Drive cylinder low register
Drive cylinder high register
Drive device head register
Drive command register
Drive status register
Drive alternate status register
Drive control register
Description
2
0
Freescale Semiconductor
Access: User read/write
0
1
Write-only
Read-only
Read-only
Write-only
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0