MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 178

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Chip Select Module
10.2.2
CS1 has a programmable address range, wait state generation, and internal/external termination. A reset
clears all chip select programming. It is multiplexed with QSPI_CS3 and GPIO28.
10.2.3
CS2 provides two separate control signals for read and write operations. These two signals go active during
CS2 cycles. IDE_DIOR can be programmed to go active on read and write cycles, or only to go active on
read cycles. IDE_DIOW operates only on write cycles.
IDE_DIOR and IDE_DIOW can be used as enables to access an IDE drive or another AT-bus peripheral.
This added functionality allows users to insert more than 16 wait states on IDE_DIOR, IDE_DIOW, and
allows dynamic cycle termination using the IDE_IORDY signal.
10.2.4
There is no physical output pin. However, the registers for CS3 are available and can be used to enable the
BUFENx outputs. These BUFENx outputs could then be used as a physical CS3. This would require
programming the CS3 registers and then setting the appropriate bits in the IDECONFIG1 register. See
Table 13-2, IDEConfig1 Register Field Descriptions
10.2.5
The OE signal enables read accesses to memory and/or peripherals. It is asserted and negated on the falling
edge of the clock. This signal is asserted when there is a match with one of the chip selects.
10.2.6
The BUFENB1/GPIO29 and BUFENB2/GPIO30 signals are intended to enable bus buffers which will
provide isolation / buffering between the MCF5253 high speed memory bus and additional external
memory mapped devices.
BUFENB1 is always active on CS0.
BUFENB2 is always inactive on CS0. It is programmable to be active on CS1, CS2, CS3 (special case)
and CS4 as desired.
10.2.7
The IDE_IORDY signal controls the insertion of wait states on CS2.
10-2
CS1/QSPI_CS3/GPIO28
CS2 — IDE_DIOR/GPIO31 and IDE_DIOW/GPIO32
CS3
Output Enable Signal OE
Buffer Enable – BUFENB1 and BUFENB2 Signals
Bus Termination Signal – IDE_IORDY
MCF5253 Reference Manual, Rev. 1
for bit 18 or 21 settings.
Freescale Semiconductor