MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 254

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

UART Modules
15.3.2.2
The receiver is enabled through the UCR located within the UART module. Functional timing information
for the receiver is shown in
of the start bit on RxD. When a transition is detected the start bit is validated 0.5 baud clock after the
transition. If RxD is sampled high, the start bit is not valid and the search for the valid start bit repeats. If
RxD is still low, a valid start bit is assumed and the receiver continues to sample the input at one-bit time
intervals at the theoretical center of the bit.
This process continues until the proper number of data bits and parity (if any) is assembled and one stop
bit is detected. Data on the RxD input is sampled on the rising edge of the programmed clock source. The
least significant bit is received first. The data is then transferred to a receiver holding register and the
RxRDY bit in the USR is set. If the character length is less than eight bits, the most significant unused bits
in the receiver holding register are cleared. The Rx RDY bit in the USR is set at the one-half point of the
stop bit.
After the stop bit is detected, the receiver immediately looks for the next start bit. However, if a nonzero
character is received without a stop bit (framing error) and RxD remains low for one-half of the bit period
after the stop bit is sampled, the receiver operates as if a new start bit is detected. The parity error (PE),
15-8
OVERRUN
(SR4)
RECEIVER
ENABLED
INTERNAL
MODULE
SELECT CS
FFULL2.5
(SR1)
NOTES:
1. TIMING SHOWN FOR UMR1[7]=1
2. TIMING SHOWN FOR UMR1[6]=0
3. CN = RECEIVED 5-8 BIT CHARACTER
RxRDY2(S
RO)
RTS1
(OP0)
Receiver
RxD
UOP1[0]=1
R = Read
Figure
|STATUS DATA|
C1
R
|
Figure 15-6. Receiver Timing Diagram
15-6. The receiver looks for a high-to-low (mark-to-space) transition
R
C2
MCF5253 Reference Manual, Rev. 1
C3
C5
LOST
C4
C5
|STATUS DATA| |STATUS DATA| |STATUS
DATA| |
C3
R R
C6
C6, C7, C8 ARE LOST DUE TO
RECEIVER DISABLED
RESET BY COMMAND
R R
C4
C7
|
R R
C8
Freescale Semiconductor
| C2