MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 526

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Universal Serial Bus Interface
24.8.6.3
The nine DWords in this area represent a transaction working space for the host controller. The general
operational model is that the host controller can detect whether the overlay area contains a description of
an active transfer. If it does not contain an active transfer, then it follows the Queue Head Horizontal Link
Pointer to the next queue head. The host controller will never follow the Next Transfer Queue Element or
Alternate Queue Element pointers unless it is actively attempting to advance the queue. For the duration
of the transfer, the host controller keeps the incremental status of the transfer in the overlay area. When the
transfer is complete, the results are written back to the original queue element.
The DWord3 of a Queue Head contains a pointer to the source qTD currently associated with the overlay.
The host controller uses this pointer to write back the overlay area into the source qTD after the transfer is
complete.
24-64
31–5 Current qTD
22–16
4–0
15–8 µFrame C-mask This field is ignored by the host controller unless the EPS field indicates this device is a low- or
Bit
7–0
Bit
µFrame S-mask Interrupt Schedule Mask. This field is used for all endpoint speeds. The software should set this field
Pointer
Name
Hub Addr
–
Name
Transfer Overlay
Current Element Transaction Descriptor Link Pointer. This field contains the address Of the current
transaction being processed in this queue and corresponds to memory address signals [31–5],
respectively.
Reserved. These bits are ignored by the host controller when using the value as an address to write data.
The actual value may vary depending on the usage.
Table 24-57. Endpoint Capabilities: Queue Head DWord 2 (continued)
This field is ignored by the host controller unless the EPS field indicates a full-or low-speed device.
The value is the USB device address of the USB 2.0 hub below which the full- or low-speed device
associated with this endpoint is attached. This field is used in the split-transaction protocol.
full-speed device and this queue head is in the periodic list. This field (along with the Active and
SplitX-state fields) is used to determine during which micro-frames the host controller should execute
a complete-split transaction. When the criteria for using this field are met, a zero value in this field has
undefined behavior. This field is used by the host controller to match against the three low-order bits
of the FRINDEX register. If the FRINDEX register bits decode to a position where the µFrame C- mask
field is a one, then this queue head is a candidate for transaction execution. There may be more than
one bit in this mask set.
to a zero when the queue head is on the asynchronous schedule. A non-zero value in this field
indicates an interrupt endpoint. The host controller uses the value of the three low-order bits of the
FRINDEX register as an index into a bit position in this bit vector. If the µFrame S-mask field has a
one at the indexed bit position then this queue head is a candidate for transaction execution. If the
EPS field indicates the endpoint is a high-speed endpoint, then the transaction executed is
determined by the PID_Code field contained in the execution area. This field is also used to support
split transaction types: Interrupt (IN/OUT). This condition is true when this field is non-zero and the
EPS field indicates this is either a full- or low-speed device. A zero value in this field, in combination
with existing in the periodic frame list has undefined results.
Table 24-58. Current qTD Link Pointer
MCF5253 Reference Manual, Rev. 1
Description
Description
Freescale Semiconductor