MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 610

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Universal Serial Bus Interface
24.12 Deviations from the EHCI Specifications
The host mode operation of the modules is nearly EHCI-compatible with few minor differences. For the
most part, the modules conform to the data structures and operations described in Section 3, “Data
Structures,” and Section 4, “Operational Model,” in the EHCI specification. The particulars of the
deviations occur in the following areas:
For the purposes of the USB OTG implementing dual-role host/device controller with support for OTG
applications, it is necessary to deviate from the EHCI specification. Device operation and OTG operation
are not specified in the EHCI and thus the implementation supported in the USB OTG module is
proprietary.
24.12.1 Embedded Transaction Translator Function
In Host mode, the USB module supports directly connected full and low speed devices without requiring
a companion controller, by including the capabilities of a USB 2.0 high speed hub transaction translator.
Although there is no separate Transaction Translator block in the system, the transaction translator
function normally associated with a high speed hub has been implemented within the DMA and Protocol
engine blocks. The embedded transaction translator function is an extension to EHCI interface, but makes
use of the standard data structures and operational models that exist in the EHCI specification to support
full and low speed devices.
24.12.1.1 Capability Registers
The following additions have been added to the capability registers to support the embedded Transaction
Translator Function:
See
24.12.1.2 Operational Registers
The addition of two-bit Port Speed (PSPD) to the PORTSCn register is added to the operational registers
to support the embedded TT:
24-148
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Section 24.6.2.3, “Host Controller Structural Parameters (HCSPARAMS)”
Embedded Transaction Translator —Allows direct attachment of FS and LS devices in host mode
without the need for a companion controller.
Device operation —In host mode, the device operational registers are generally disabled and thus
device mode is mostly transparent. However, there are a couple exceptions and they are
documented in the following sections.
Embedded design interface—The USB module does not have a PCI Interface and therefore the PCI
configuration registers described in the EHCI specification are not applicable.
N_TT added to HCSPARAMS
N_PTT added to HSCPARAMS
MCF5253 Reference Manual, Rev. 1
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—
Host Controller Structural Parameters
Host Controller Structural Parameters
for usage information.
Freescale Semiconductor