MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 189

IC MPU 32BIT 140MHZ 225-MAPBGA

MCF5253CVM140

Manufacturer Part Number
MCF5253CVM140
Description
IC MPU 32BIT 140MHZ 225-MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF525xr

Specifications of MCF5253CVM140

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
140MHz
Connectivity
CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
Peripherals
DMA, WDT
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
225-MAPBGA
Family Name
MCF5xxx
Device Core
ColdFire V2
Device Core Size
32b
Frequency (max)
140MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.2/3.3V
Operating Supply Voltage (max)
1.32/3.6V
Operating Supply Voltage (min)
1.08/3V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
225
Package Type
MA-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant

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When the timer reaches the reference value, the REF bit in the TER register is set and issues an interrupt
if the output reference interrupt (ORI) enable bit in TMR is set.
11.5.3
Timer0 can send an output signal on the timer output (TOUT0) pin when it reaches the reference value as
selected by the output mode (OM) bit in the TMR. This signal can be an active-low pulse or a toggle of
the current output under program control.
11.6
Users can modify the timer registers at any time.
11.6.1
The TMR is a 16-bit memory-mapped register. This register programs the various timer modes and is
cleared by reset.
Freescale Semiconductor
Bit Name
Timer 0 Address
Address MBAR+$140
15–8
7–6
MBAR+$14C
CE
MBAR+$140
MBAR+$144
MBAR+$148
MBAR+$151
PS
Reset
W
R
General-Purpose Timer Memory Map and Register Definitions
MBAR+$180
Configuring the Timer for Output Mode (TIMER0)
Timer Mode Registers (TMR0, TMR1)
15
The Prescaler Value is programmed to divide the clock input by values from 1 to 256. The value 00000000 divides
the clock by 1; the value 11111111 divides the clock by 256.
Prescalar value = $[PS7 – PS0] + 1
These bits have no function and should be set to 00.
0
14
0
PRESCALER VALUE (PS7–PS0)
Timer 1 Address
13
Table 11-2. Timer Mode Register (TMRn) Field Descriptions
0
MBAR+$18C
MBAR+$180
MBAR+$184
MBAR+$188
MBAR+$191
Table 11-1. Memory Map for General-Purpose Timers
12
0
Figure 11-2. Timer Mode Register (TMRn)
11
0
MCF5253 Reference Manual, Rev. 1
10
0
9
0
Table 11-1
8
0
Reserved
Description
CE1
0
7
Timer Reference Register (TRRn)
Timer Capture Register (TCRn)
shows the timer memory map.
Timer Mode Register (TMRn)
CE0
Timer Module Registers
0
6
Timer Counter (TCNn)
OM
0
5
Access: Supervisor or User read/write
ORI
0
4
Timer Event Register (TERn)
FRR CLK1 CLK0 RESET
General Purpose Timer Modules
0
3
0
2
0
1
0
0
11-3

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