MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 240

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

DMA Controller
14.4.7
The DMA Interrupt Vector Register (DIVR) is an 8-bit register, which is driven out onto the bus in
response to an internal acknowledge cycle.
14-12
Address MBAR + $314
DONE
Field
REQ
Bit 7
BES
BED
BSY
Reset
CE
6
5
4
3
2
1
0
W
R
MBAR + $354
MBAR + $394
MBAR + $3D4
Reserved
A configuration error results when either the number of bytes represented by the BCR is not consistent with the
requested source or destination transfer size. Configuration error can also result from the SAR or DAR containing
an address that does not match the requested transfer size for the source or destination. The bit is cleared during a
hardware reset or by writing a one to DSR[DONE].
0 No configuration error exists.
1 A configuration error has occurred.
Bus error on source.
0 No bus error occurred.
1 The DMA channel terminated with a bus error either during the read portion of a transfer.
Bus error on destination.
0 No bus error occurred.
1 The DMA channel terminated with a bus error during the write portion of a transfer.
Reserved
Request
0 There is no request pending or the channel is currently active. The bit is cleared when the channel is selected.
1 The DMA channel has a transfer remaining and the channel is not selected.
Busy
0 DMA channel is inactive. This bit is cleared when the DMA has finished the last transaction.
1 This bit is set the first time the channel is enabled after a transfer is initiated.
The transaction done bit may be read or written and is set when all DMA controller module transactions have
completed normally, as determined by the transfer count and error conditions. When the BCR reaches zero, DONE
is set at the successful conclusion of the final transfer.
Writing a 1 to this bit clears all DMA status bits and therefore can be used as an interrupt handler to clear the DMA
interrupt and error bits. The DONE bit can also be used to abort a transfer in progress by resetting the status bits.
The DONE bit is self clearing. Therefore, writing a 0 to it has no effect.
0 Writing or reading a 0 has no effect whatsoever.
1 DMA transfer completed.
DMA Interrupt Vector Register
0
7
Table 14-12. DMA Status Register (DSR) Field Descriptions
0
6
Figure 14-10. DMA Interrupt Vector Register (DIVR)
MCF5253 Reference Manual, Rev. 1
0
5
INTERRUPT VECTOR BITS
0
4
Description
1
3
1
2
Freescale Semiconductor
Access: User read/write
1
1
1
0