MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 614

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Universal Serial Bus Interface
24.12.1.5.5 Multiple Transaction Translators
The maximum number of embedded Transaction Translators that is currently supported is one as indicated
by the N_TT field in the HCSPARAMS register. See
Parameters (HCSPARAMS),”
24.12.2 Device Operation
The co-existence of a device operational controller within the USB OTG module has little effect on EHCI
compatibility for host operation. However, given that the controller is initialized in neither host nor device
mode, the USBMODE register must be programmed for host operation before the EHCI host controller
driver can begin EHCI host operations.
24.12.3 Non-Zero Fields the Register File
Some of the reserved fields and reserved addresses in the capability registers and operational registers have
use in device mode, the following must be adhered to:
24.12.4 SOF Interrupt
The SOF interrupt is a free running 125 µsec interrupt for host mode. EHCI does not specify this interrupt,
but it has been added for convenience and as a potential software time base. Note that the free running
interrupt is shared with the device-mode start-of-frame interrupt. See
24-152
•
•
— Complete-split transaction searching.
Write operations to all EHCI reserved fields (some of which are device fields in the USB OTG
module) in the operation registers should always be written to zero. This is an EHCI requirement
of the device controller driver that must be adhered to.
Read operations by the module must properly mask EHCI reserved fields (some of which are
device fields in the USB OTG module registers).
Limiting the number of tracking pipes in the EMBedded
impose the restriction that no more than 4 periodic transactions
(INTERRUPT/ISOCHRONOUS) can be scheduled through the
embedded-tt per frame. The number 16 was chosen in the USB specification
because it is sufficient to ensure that the high-speed to full-speed periodic
pipeline can remain full. Keeping the pipeline full puts no constraint on the
number of periodic transactions that can be scheduled in a frame and the
only limit becomes the flight time of the packets on the bus.
There is no data schedule mechanism for these transactions other than the
microframe pipeline. The embedded TT assumes the number of packets
scheduled in a frame does not exceed the frame duration (1 msec) or else
undefined behavior may result.
for more information.
MCF5253 Reference Manual, Rev. 1
CAUTION
NOTE
Section 24.6.2.3, “Host Controller Structural
Section 24.6.3.2, “USB Status
—
TT to four (4) will
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