MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 412

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

IEEE 1149.1 Test Access Port (JTAG)
21.3
The JTAG operation on the MCF5253 is enabled when TEST[2:0]= 000, in which case the external pin
descriptions in
(TCK/TMS/TDI/TDO/TRST) are interpreted as the debug port pins.
21-2
TRST
TMS
TCK
TDI
JTAG Signal Descriptions
TMS
TCK
Pin
V+
V+
V+
Table 21-1
A test clock input that synchronizes test logic operations
A test mode select input with a default internal pullup resistor that is sampled on the rising
edge of TCK to sequence the TAP controller
BYPASS
apply.Otherwise, the JTAG Test Access Port signals
BOUNDARY SCAN REGISTER
IDCODE REGISTER
4-BIT INSTRUCTION DECODE
4-BIT INSTRUCTION REGISTER
Figure 21-1. JTAG Test Logic Block Diagram
TEST DATA REGISTERS
TAP
CONTROLLER
Table 21-1. JTAG Pin Descriptions
MCF5253 Reference Manual, Rev. 1
Description
M
U
X
MUX
Freescale Semiconductor
TDO