MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 236

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

DMA Controller
The DONE bit in the DMA status register
When a transfer sequence is initiated and the BCR contains a value that is not divisible by 16, 4, or 2 when
the DMA is configured for line, longword, or word transfers, respectively, the configuration error bit (CE)
in the DMA status register (DSR) is set and the transfer does not take place. Refer to
Status Register,”
14.4.5
The DMA control register (DCR) sets the configuration of the DMA controller module. Depending on the
state of the BCR24BIT in the MPARK register in the SIM module, the DMA control register looks slightly
different. Specifically, the AT bit (DCR[15]) is included when BCR24BIT = 1, providing greater flexibility
in DMA transfer acknowledge.
14-8
Address MBAR + $30C
Reset
Reset
W
W
R
R
MBAR + $34C
MBAR + $38C
MBAR + $3CC
BCR15 BCR14 BCR13 BCR12 BCR11 BCR10
31
15
DMA Control Register
–
–
for more details.
30
14
–
–
29
13
–
–
Figure 14-7. Byte Count Register (BCR)—BCR24BIT = 0
28
12
–
–
27
11
–
–
MCF5253 Reference Manual, Rev. 1
26
10
–
–
(Table
BCR9
25
–
–
9
14-9) is set when the entire block transfer is complete.
BCR8
24
–
–
8
BCR7
23
–
–
7
BCR6
22
–
–
6
BCR5
21
–
5
–
BCR4
20
–
–
4
Section 14.4.6, “DMA
BCR3
19
–
–
3
Freescale Semiconductor
Access: User read/write
BCR2
18
–
–
2
BCR1
17
–
–
1
BCR0
16
–
–
0