MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 286

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Queued Serial Peripheral Interface (QSPI) Module
The RAM is divided into three segments with 16 addresses each:
The transmit and command RAM are write-only by the user. The receive RAM is read-only by the user.
Figure 16-2
The command and data RAM in the QSPI is indirectly accessible with QDR and QAR as 48 separate
locations that comprise 16 words of transmit data, 16 words of receive data and 16 bytes of commands.
A write to QDR causes data to be written to the RAM entry specified by QAR[ADDR] and causes the
value in QAR to increment. Correspondingly, a read at QDR returns the data in the RAM at the address
specified by QAR[ADDR]. This also causes QAR to increment. A read access requires a single wait state.
16-4
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Receive data RAM, the initial destination for all incoming data
Transmit data RAM, a buffer for all out-bound data
Command RAM, where commands are loaded
shows the RAM configuration. The RAM contents are undefined immediately after a reset.
Address
Relative
0x0F
0x1F
0x2F
0x00
0x01
0x10
0x11
0x20
0x21
MCF5253 Reference Manual, Rev. 1
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Figure 16-2. QSPI RAM Model
Register
QTR15
QRR15
QCR15
QRR0
QRR1
QCR0
QCR1
QTR0
QTR1
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Command RAM
Transmit RAM
Receive RAM
16 bits wide
16 bits wide
8 bits wide
Function
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