MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 115

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Figure 7-7
SRAS-to-SCAS delay (t
Freescale Semiconductor
D[31:16]
SD_CS0
SDRAS
SDCAS
A[31:0]
UDQM
SDWE
LDQM
BCLK
shows the burst write operation. In this example, DACR[CASL] = 01, which creates an
Data is available upon SCAS assertion and a burst write cycle completes
two cycles sooner than a burst read cycle with the same t
cycle is initiated sooner, but cannot begin an SDRAM cycle until the
precharge-to-
actv
tRCD = 2
RCD
Row
nop
) of 2 BCLK cycles.
ACTV
Figure 7-6. Burst Read SDRAM Access
delay completes.
Column Column Column
MCF5253 Reference Manual, Rev. 1
t
CASL
= 1
read
NOTE
Column
nop
RCD.
Synchronous DRAM Controller Module
nop
t
The next bus
EP
pall
7-11