MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 429

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

All transfers between FIFO and host IP or DMA IP bus are zero wait states transfer, so high speed transfer
between FIFO and DMA/host bus is possible.
When a PIO access is performed during a running DMA transfer, the DMA transfer will be paused, the
PIO access done, and the DMA transfer will resume again.
23.3.1
The interface offers two operation modes that can be used together:
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The PIO mode is a slow protocol, mainly intended to program the ATA disc drive, but also possible
to use to transfer data to/from the disc drive. During PIO mode, the FIFO is not active.
Second protocol. This protocol is the DMA mode access. DMA mode is started by the ATA
interface after receiving a DMA request from the drive, and only if the ATA interface has been
programmed to accept the DMA request. In DMA mode, either multiword DMA or ultra DMA
protocol is used on the ATA bus. Once started, data transfer is organized between the ATA bus and
the FIFO. Data transfer will pause to prevent FIFO overflow / FIFO underflow. Data transfer will
resume when there is again space in the FIFO, or when the FIFO has been refilled. During DMA
transfer, there is no direct interface between the ATA bus and the host IP or host DMA IP bus.
Instead, the transfer takes place between the ATA bus and the FIFO; the FIFO informs the host
DMA unit when it needs to be refilled or emptied. In this case, it sends an ALARM flag to the host
DMA. When the host DMA receives the fifo_tx_alarm, it should write some data to the FIFO.
(typically 32 bytes). When the host DMA receives the fifo_rcv_alarm, it should read some data
from the FIFO (typically 32 bytes). The FIFO filling level at which the alarms are produced, is
programmable. For completeness, there is a third alarm associated with the host DMA operation
fifo_txfer_end_alarm. This alarm signals the end of the transfer, and requests the smart DMA to
take steps to complete the transfer: transfer the bytes remaining in the FIFO to the host memory,
and inform the host CPU the transfer is completed.
PIO Mode
An access to the ATA bus in PIO mode occurs whenever a ATA PIO register is read or written by
the host CPU or the host (smart) DMA unit. During a PIO transfer the incoming IP bus cycle is
translated to an ATA PIO bus cycle by the ATA protocol engine. No buffering of data occurs, so
the host CPU or host DMA cycle is stalled until the ATA bus read data is available on read, or is
stalled until the IP bus data can we put on the ATA bus during write.
PIO accesses can be done to the bus at any time, even during a running ATA DMA transfer. In this
case, the DMA transfer is paused, the PIO cycle is completed, and the DMA transfer is resumed.
DMA Mode
In DMA mode, data is transferred between the ATA bus and the FIFO. Two different DMA
protocols are supported on the ATA bus: ultra DMA mode and multiword DMA mode. Selection
is made using a control register bit.
A DMA transfer will be started when DMA mode transfer has been enabled by writing some
control bit, and when the drive connected to the ATA bus pulls its DMARQ line high.
During an ATA bus DMA transfer, data is transferred between the ATA bus and the FIFO. The
transfer will pause to avoid FIFO overflow and FIFO underflow.
Modes of Operation
MCF5253 Reference Manual, Rev. 1
Advanced Technology Attachment Controller (ATA)
23-3