MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 545

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Alternatively, a host controller implementation is allowed to traverse the entire asynchronous schedule list
(for example, observed the head of the queue (twice)) before setting the Advance on Async status bit.
The software may re-use the memory associated with the removed queue heads after it observes the
Interrupt on Async Advance status bit is set, following assertion of the doorbell. The software should
acknowledge the Interrupt on Async Advance status as indicated in the USBSTS register, before using the
doorbell handshake again
24.9.9.3
EHCI uses two bits to detect when the asynchronous schedule is empty. The queue head data structure (see
Figure
the head of the reclaim list. host controller also keeps a 1-bit flag in the USBSTS register (Reclamation)
that is cleared when the host controller observes a queue head with the H-bit set. The reclamation flag in
the status register is set when any USB transaction from the asynchronous schedule is executed (or
whenever the asynchronous schedule starts, see
Start Event.”
If the controller ever encounters an H-bit of one and a Reclamation bit of zero, the controller simply stops
traversal of the asynchronous schedule.
An example illustrating the H-bit in a schedule is shown in
Freescale Semiconductor
24-41) defines an H-bit in the queue head, which allows the software to mark a queue head as being
HC State
Empty Asynchronous Schedule Detection
A
A
Memory State
Before Unlink
B
Async-Advance Doorbell = 0
Figure 24-49. Generic Queue Head Unlink Scenario
USBCMD Interrupt on
C
HC State
MCF5253 Reference Manual, Rev. 1
D
A
USBSTS Interrupt on Async-Advance = 1
D
Async-Advance Doorbell = 0
After Doorbell
Memory State
B
USBCMD Interrupt on
Section 24.9.9.4, “Asynchronous Schedule Traversal:
C
HC State
Figure
After Unlink (B, C) and at Doorbell
A
A
USBSTS Interrupt on Async-Advance = 0
D
24-50.
Async-Advance Doorbell = 1
Memory State
B
USBCMD Interrupt on
C
Universal Serial Bus Interface
D
24-83