MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 29

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Chapter 21, “IEEE 1149.1 Test Access Port
Chapter 22, “USB, ATA DMA, and Clock Integration
Chapter 23, “Advanced Technology Attachment Controller
Chapter 24, “Universal Serial Bus
Chapter 25, “FlexCAN
Chapter 26, “Real-Time
Revision History
The table below summarizes revisions to this document since the previous release (Rev. 0).
Suggested Reading
Provide the full title, name of author, edition, and year of publication for any book you suggest as a
supplement to this one.
PowerPC AIX Version 4 Application Binary Interface, 1st ed., April 1992.
The KornShell Command and Programming Language, Morris Bolsky and David Korn (Prentice Hall:
1989).
Freescale Semiconductor
Chapter 17, “Audio Interface
Chapter 13, “IDE and Flash
Chapter 24, “Universal
Serial Bus
Media
Module
Chapter
Interface”
Interface”
(AIM)”
Module”:This chapter discusses the modes of operation, signals, memory map,
debug mode (BDM), and real-time debug support. The memory map, register
definitions, and Debug support operation are provided.
descriptions, TAP controller, memory map, register definitions, and how to
disable the standard operation.
register definitions, and functional description of the integration module.
operation, signal descriptions, memory map, register definitions, timing
parameters and functional description of the ATA interface.
interface of the MCF5253. The content includes the operation, signal descriptions,
host data structures, and host operations. Also provided is the device operational
model and deviations from the host mode of operation.
register definitions, and the functional and initialization sequence of the FlexCAN
controller.
register definitions, and functional descriptions of the Real-Time Clock.
Clock”:
In Section “Send Command to Card (Receive Multiple Data Blocks and Status)” changed first
“read FLASHMEDIADATA2” to “write FLASHMEDIADATA2”
Corrected inconsistent register locations
Corrected bit description of HCSPARAMS[N_TT and P_TT] from “This field is always 1” to “This
field is always 0”
This chapter provides the external signal descriptions, memory map,
Interface”:
MCF5253 Reference Manual, Rev. 1
(JTAG)”:
Revision History
This chapter describes the universal serial bus (USB)
This chapter discussed the JTAG signal
Module”:This chapter includes the memory map,
Substantive Changes
(ATA)”:This chapter discusses the modes of
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