MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 520

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Universal Serial Bus Interface
24.8.5.3
The third DWord of a queue element transfer descriptor contains most of the information the host
controller requires to execute a USB transaction (the remaining endpoint-addressing information is
specified in the queue head). Note that some of the field descriptions in
defined in the queue head. See
24-58
30–16
14–12
4–1
Bit
Bit
31
15
0
Total Bytes
to Transfer
C_Page
Name
Name
ioc
T
dt
–
Table 24-52. qTD Alternate Next Element Transfer Pointer (DWord 1) (continued)
qTD Token
Data Toggle. This is the data toggle sequence bit. The use of this bit depends on the setting of the Data
Toggle Control bit in the queue head.
Total Bytes to Transfer. This field specifies the total number of bytes to be moved with this transfer
descriptor. This field is decremented by the number of bytes actually moved during the transaction, only
on the successful completion of the transaction. The maximum value the software may store in this field is
5
field is zero when the host controller fetches this transfer descriptor (and the active bit is set), the host
controller executes a zero-length transaction and retires the transfer descriptor. It is not a requirement for
OUT transfers that Total Bytes To Transfer be an even multiple of QH[Maximum Packet Length]. If the
software builds such a transfer descriptor for an OUT transfer, the last transaction will always be less than
QH[Maximum Packet Length]. Although it is possible to create a transfer up to 20K this assumes the page
is 0. When the offset cannot be predetermined, crossing past the 5th page can be guaranteed by limiting
the total bytes to 16K. Therefore, the maximum recommended transfer is 16K(0x4000).
should issue an interrupt at the next interrupt threshold.
Current Page. This field is used as an index into the qTD buffer pointer list. Valid values are in the range
0x0 to 0x4. The host controller is not required to write this field back when the qTD is retired.
Interrupt On Complete. If this bit is set, it specifies that when this qTD is completed, the Host Controller
Reserved. These bits are reserved and their value has no effect on operation.
Terminate. This bit indicates to the Host Controller that there are no more valid entries in the queue.
0 Pointer is valid (points to a valid Transfer Element Descriptor).
1 Pointer is invalid.
×
4K (0x5000). This is the maximum number of bytes 5 page pointers can access. If the value of this
Section 24.8.6, “Queue Head,”
Table 24-53. qTD Token (DWord 2)
MCF5253 Reference Manual, Rev. 1
Description
Description
for more information on these fields.
Table 24-53
Freescale Semiconductor
reference fields