MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 560

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Universal Serial Bus Interface
Figure 24-56
each split transaction. The first is a single start-split transaction, which occurs when the SplitXState is at
Do_Start and the single bit in cMicroFrameBit has a corresponding bit active in QH[S-mask]. The
transaction translator does not acknowledge the receipt of the periodic start-split, so the host controller
unconditionally transitions the state to Do_Complete. Due to the available jitter in the transaction
translator pipeline, there will be more than one complete-split transaction scheduled by the software for
the Do_Complete state. This translates simply to the fact that there are multiple bits set in the QH[C-mask]
field.
The host controller keeps the queue head in the Do_Complete state until the split transaction is complete
(see definition below), or an error condition triggers the three-strikes-rule (for example, after the host tries
the same transaction three times, and each encounters an error, the host controller stops retrying the bus
transaction and halts the endpoint, thus requiring the system software to detect the condition and perform
system-dependent recovery).
24.9.12.2.6 Periodic Interrupt—Do-Start-Split
This is the state the software must initialize a full- or low-speed interrupt queue head StartXState bit. This
state is entered from the Do_Complete Split state only after the split transaction is complete.
24-98
corresponds to the current micro-frame number. For example, if the current micro-frame is 0, then
cMicroFrameBit will equal 0b0000_0001.
The variable cMicroFrameBit is used to compare against the S-mask and C-mask fields to
determine whether the queue head is marked for a start- or complete-split transaction for the
current micro-frame.
CERR –– > 0
Data Loss
Babble
STALL
.or.
.or.
.or.
illustrates how a complete interrupt split transaction is managed. There are two phases to
Queue
State
Halt
Figure 24-56. Split Transaction State Machine for Interrupt
Queue
Active
State
Transaction
Complete
MDATA
NYET
Split
.or.
MCF5253 Reference Manual, Rev. 1
cMicroFrameBit)
!(QH.S-Mask &
Complete-
Start-
Split
Split
Do
Do
XactErr
cMicroFrameBit)
(QH.S-Mask &
* Issue Start-Split Transaction
* Tag QH with Frame Number According
* QH.C-prog-mask = zero(0x00)
to the Frame Tag Rules **(1,3)
Decrement Error Counter (CERR)
* Issue Complete-Split Transaction
* Tag QH with Frame Number According
* C-prog-mask |= cMicroFrameBit
to the **Sframe Tag Rules
and Do Immediate Retry
of Complete-Split
CheckPreviousBit(QH.C-prog-mask,
(FRINDEX[7:3] .eq. QH.FrameTag)
(QH.C-Mask & cMicroFrameBit)
QH.C-Mask, cMicroFrameBit)
.and.
.and.
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