MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 500

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Universal Serial Bus Interface
24.6.3.16 Endpoint Setup Status Register (ENDPTSETUPSTAT)—Non-EHCI
This register is not defined in the EHCI specification. This register contains the endpoint setup status. It is
used only in device mode.
24-38
SLOM
Field
SDIS
31–5 Reserved.
1–0
CM
ES
4
3
2
Stream Disable.
In host mode, setting this bit to a 1 ensures that overruns/underruns of the latency FIFO are eliminated for low
bandwidth systems where the RX and TX buffers are sufficient to contain the entire packet. Enabling stream disable
also has the effect of ensuring the TX latency is filled to capacity before the packet is launched onto the USB.
Note: Time duration to pre-fill the FIFO becomes significant when stream disable is active. See TXFILLTUNING to
Also note that in systems with high system bus utilization, setting this bit will ensure no overruns or underruns during
operation, at the expense of link utilization. For those who desire optimal link performance, SDIS can be left clear, and
the rules used under the description of the TXFILLTUNING register to limit underruns/overruns.
1 Active
0 Inactive
In device mode (), setting this bit to a 1 disables double priming on both RX and TX for low bandwidth systems. This
mode ensures that when the RX and TX buffers are sufficient to contain an entire packet that the standard double
buffering scheme is disabled to prevent overruns/underruns in bandwidth limited systems.
Note: In High Speed Mode, all packets received will be responded to with a NYET handshake when stream disable is
Setup Lockout Mode (). For the USB OTG module in device mode, this bit controls behavior of the setup lock
mechanism. See
1 Setup Lockouts Off(DCD requires use of Setup Data Buffer Tripwire in USBCMD).
0 Setup Lockouts On.
Endian select. Controls the byte ordering of the transfer buffers to match the host microprocessor bus architecture. The
bit fields in the register interface and the DMA data structures (including the setup buffer within the device QH) are
unaffected by the value of this bit, because they are based upon 32-bit words.
0 Little endian. First byte referenced in least significant byte of 32-bit word.
1 Big endian. First byte referenced in most significant byte of 32-bit word.
Note: For proper operation, this bit must be set for this ColdFire device.
Controller Mode.
This register can be written only once after reset. If it is necessary to switch modes, the software must reset the
controller by writing to the RESET bit in the USBCMD register before reprogramming this register.
00 Idle (Default for combination host/device).
01 Reserved.
10 Device Controller (Default for device only controller).
11 Host Controller (Default for host only controller).
The USB OTG module defaults to the idle state and needs to be initialized to the desired operating mode after reset.
characterize the adjustments needed for the scheduler when using this feature.
active.
Table 24-29. USB Mode (USBMODE) Register Field Descriptions
Section 24.11.3.5, “Control Endpoint Operation Model.”
MCF5253 Reference Manual, Rev. 1
Description
Freescale Semiconductor