MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 123

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

7.6.3
As shown in
block of each 1 Mbyte partition in the SDRAM (each 16 Mbyte). The starting address of the SDRAM is
0xFF80_0000. Continuous page mode feature is used.
This configuration results in a value of DACR0 = 0xFF88_1224, as described in
Freescale Semiconductor
31–18
17–16
13–12
CASL
Field Setting
10–8
CBM
RE
BA
15
14
11
Setting
Setting
(hex)
(hex)
Field
Field
1 MB
010
01
–
–
0
–
–
RE
31
15
DACR Initialization
0
Figure
Base address. So DACR0[31–16] = 0xFF88, which places the starting address of the SDRAM accessible
memory at 0xFF88_0000.
Reserved. Don’t care.
0, which keeps auto-refresh disabled because registers are being set up at this time.
Reserved. Don’t care.
Indicates a delay of data 1 cycle after CAS is asserted.
Reserved. Don’t care.
Command bit is pin 19 and bank selects are 20 and up.
512 Kbyte
512 Kbyte
30
14
–
Bank 0
7-14, in this example the SDRAM is programmed to access only the second 512 Kbyte
F
1
29
13
CASL
01
1 MB
28
12
Figure 7-15. DACR Register Configuration
Table 7-15. DACR Initialization Values
Figure 7-14. SDRAM Configuration
27
11
–
MCF5253 Reference Manual, Rev. 1
512 Kbyte
512 Kbyte
26
10
Bank 1
1111_1111_1000_10
SDRAM Component
F
2
CBM
010
25
9
BA
24
1 MB
8
Description
23
–
7
IMRS
512 Kbyte
512 Kbyte
22
0
6
Bank 2
8
2
21
5
PS
10
Synchronous DRAM Controller Module
20
1 MB
4
Accessible
Memory
Table
IP
19
0
3
7-15.
512 Kbyte
512 Kbyte
PM
18
1
Bank 3
2
8
4
17
–
–
1
16
–
–
0
7-19