MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 304

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Audio Interface Module (AIM)
17.4
The interrupts of the audio interface use vectors 0–31 of the interrupt controller. There are two sets of
registers associated with interrupt operation.
Every pending audio interrupt will show up as a ‘1’ in register InterruptStat or InterruptStat3. The interrupt
will cause the associated interrupt to go active if the corresponding bit in InterruptEn is set to ‘1‘. Most
interrupts are cleared by writing a ‘1’ to the corresponding bit in InterruptClear register.
17-6
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
UCHANTX NEXTFIRST U Channel transmit register next byte will be first
EBU1VALNOGOOD
U1CHANRCVFULL
UCHANTXEMPTY
UCHANTXUNDER
Audio Interrupt Mask and Status Register Descriptions
Interrupt Name
EBU1SYMERR
EBUTXRESYN
IIS1TXRESYN
IIS2TXRESYN
EBUTXUNOV
EBU1BITERR
IIS1TXUNOV
IIS2TXUNOV
MBAR2 + 0x94
MBAR2 + 0x97
MBAR2 + 0x98
MBAR2 + 0x9B
MBAR2 + 0x9
MBAR2 + 0x9B
MBAR2 + 0xE4
MBAR2 + 0xE7
MBAR2 + 0xE0
MBAR2 + 0xE3
MBAR2 + 0xE0
MBAR2 + 0xE3
EBU1CNEW
Address
InterruptClear3
I
I
I
I
IEC958 transmit FIFO under/over
IEC958 transmit FIFO resync
IEC958-1 receiver new C channel received
IEC958-1 receiver validity bit not set
IEC958-1 receiver symbol error
IEC958-1 receiver parity bit error
U Channel transmit register is empty
U Channel transmit register underrun
U1Channel receive register full
InterruptClear
InterruptStat3
2
2
2
2
InterruptStat
InterruptEn3
InterruptEn
S 1 transmit FIFO under/over
S 1 transmit FIFO resync
S 2 transmit FIFO under/over
S 2 transmit FIFO resync
Table 17-3. Interrupt Register Description
Name
Table 17-2. Interrupt Register Addresses
MCF5253 Reference Manual, Rev. 1
Width
Description
32
32
32
32
32
32
Interrupt enable register
Interrupt enable register
Interrupt status register
Interrupt status register
Interrupt clear register
Interrupt clear register
Description
Vector
Reset
Value
31
30
29
28
27
26
25
24
23
23
21
20
19
18
0
–
–
–
–
–
Freescale Semiconductor
Access
R/W
R/W
W
W
R
R
write to Tx reg
How to Clear
write to tx reg
read Rcv reg
reg. IntClear
reg. IntClear
reg. IntClear
reg. IntClear
reg. IntClear
reg. IntClear
reg. IntClear
reg. IntClear
reg. IntClear
reg. IntClear
reg. IntClear