MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 94

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Instruction Cache
5.5.2
5.5.2.1
The CACR controls the operation of the instruction cache. The CACR provides a set of default memory
access attributes used when a reference address does not map into the spaces defined by the ACRs.
The CACR is a 32-bit write-only supervisor control register. It is accessed in the CPU address space using
the MOVEC instruction with an Rc encoding of $002. The CACR can be read when in Background Debug
mode (BDM). At system reset, the entire register is cleared.
5-6
Bit Name
Address MOVEC with $002
CENB
30–29
26–25
CFRZ
CPDI
Reset
Reset
31
28
27
W
W
R
R
CENB
The Cache Enable bit generally provides longword references used for sequential fetches. If the processor branches
to an odd word address, a word-sized fetch is generated. The memory array of the instruction cache is enabled only
if CENB is asserted.
0 Cache disabled
1 Cache enabled
Reserved, should be cleared.
When the disable CPUSHL Invalidation instruction is executed, the cache entry defined by bits [8:4] of the address
is invalidated if CPDI = 0. If CPDI = 1, no operation is performed.
0 Enable invalidation
1 Disable invalidation
be initiated and loaded into the line-fill buffer, but a valid cache entry can not be overwritten. If a given cache location
is invalid, the contents of the line-fill buffer can be written into the memory array while CFRZ is asserted.
0 Normal operation
1 Freeze valid cache lines
Reserved, should be cleared.
The Cache Freeze bit allows users to freeze the contents of the cache. When CFRZ is asserted line fetches can
31
15
Instruction Cache Register
0
0
Cache Control Register
30
14
0
0
29
13
0
0
CPDI
Table 5-4. Cache Control Register Field Descriptions
28
12
0
0
Figure 5-2. Cache Control Register (CACR)
CFRZ
27
11
0
0
MCF5253 Reference Manual, Rev. 1
CEIB
26
10
0
0
DCM
25
0
0
9
DBWE
Description
CINV
24
0
0
8
23
0
0
7
DWP
22
0
6
0
21
0
5
0
20
0
0
4
19
0
0
3
Freescale Semiconductor
Access: User read/write
18
0
2
0
CLNF1
17
0
0
1
CLNF2
16
0
0
0