MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 399

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

20.4.1.2
20.4.1.2.1
The debug module implementation provides a common hardware structure for both BDM and breakpoint
functionality. Several structures are used for both BDM and breakpoint purposes.
the shared hardware structures.
The shared use of these hardware structures means the loading of the register to perform any specified
function is destructive to the shared function. For example, if an operand address breakpoint is loaded into
the debug module, a BDM command to access memory overwrites the breakpoint. If a data breakpoint is
configured, a BDM write command overwrites the breakpoint contents.
20.5
In addition to the existing BDM commands that provide access to the processor’s registers and the memory
subsystem, the debug module contains nine registers to support the required functionality. All of these
registers are treated as 32-bit quantities, regardless of the actual number of bits in the implementation. The
registers, known as the debug control registers, are accessed through the BDM port using two new BDM
commands: WDMREG and RDMREG. These commands contain a 4-bit field, DRc, which specifies the
particular register being accessed.
These registers are also accessible from the processor’s supervisor programming model through the
execution of the WDEBUG instruction. Thus, the breakpoint hardware within the debug module may be
accessed by the external development system using the serial interface, or by the operating system running
on the processor core. It is the responsibility of the software to guarantee that all accesses to these resources
are serialized and logically consistent. The hardware provides a locking mechanism in the CSR to allow
the external development system to disable any attempted writes by the processor to the breakpoint
registers (setting IPW = 1). The BDM commands must not be issued if the ColdFire processor is accessing
the debug module registers using the WDEBUG instruction.
Freescale Semiconductor
Debug Module Memory Map and Register Definitions
Register
Debug Module Hardware
ABHR
AATR
Reuse of Debug Module Hardware (Rev. A)
DBR
Bus Attributes for All Memory Commands
Address for All Memory Commands
Data for All BDM Write Commands
Table 20-18. Shared BDM/Breakpoint Hardware
MCF5253 Reference Manual, Rev. 1
BDM Function
Address for Address Breakpoint
Attributes for Address Breakpoint
Data for Data Breakpoint
Breakpoint Function
Background Debug Mode (BDM) Interface
Table 20-18
identifies
20-29