MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 531

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Universal Serial Bus Interface
management policy implemented in a particular operating system. When the system software intends to
suspend the bus, it should suspend the enabled port, then shut off the controller by setting the Run/Stop bit
in the USBCMD register to a zero.
When a wake event occurs the system will resume operation, and the system software must set the
Run/Stop bit to a one and resume the suspended port.
24.9.4.1
Port Suspend/Resume
The system software places the USB into suspend mode by writing a one into the appropriate PORTSC
Suspend bit. The software must only set the Suspend bit when the port is in the enabled state (Port Enabled
bit is a one).
The host controller may evaluate the Suspend bit immediately or wait until a micro-frame or frame
boundary occurs. If evaluated immediately, the port is not suspended until the current transaction (if one
is executing) completes. Therefore, there may be several micro-frames of activity on the port until the host
controller evaluates the Suspend bit. The host controller must evaluate the Suspend bit at least every frame
boundary.
The system software can initiate a resume on the suspended port by writing a one to the Force Port Resume
bit. The software should not attempt to resume a port unless the port reports that it is in the suspended state.
If the system software sets the Force Port Resume bit when the port is not in the suspended state, the
resulting behavior is undefined. In order to assure proper USB device operation, the software must wait
for at least 10 milliseconds after a port indicates that it is suspended (Suspend bit is a one) before initiating
a port resume via the Force Port Resume bit. When Force Port Resume bit is set, the host controller sends
resume signaling down the port. The system software times the duration of the resume (nominally 20
milliseconds) then clears the Force Port Resume bit. When the host controller receives the write to
transition Force Port Resume to zero, it completes the resume sequence as defined in the USB
specification, and clears both the Force Port Resume and Suspend bits. Software-initiated port resumes do
not affect the Port Change Detect bit in the USBSTS register nor do they cause an interrupt if the Port
Change Interrupt Enable bit in the USBINTR register is a one. When a wake event occurs on a suspended
port, the resume signaling is detected by the port and the resume is reflected downstream within 100 µsec.
The port's Force Port Resume bit is set and the Port Change Detect bit in the USBSTS register is set. If the
Port Change Interrupt Enable bit in the USBINTR register is a one the host controller issues a hardware
interrupt.
The system software observes the resume event on the port, delays a port resume time (nominally 20
milliseconds), then terminates the resume sequence by clearing the Force Port Resume bit in the port. The
host controller receives the write of zero to Force Port Resume, terminates the resume sequence and clears
the Force Port Resume and Suspend port bits. The software can determine that the port is enabled (not
suspended) by sampling the PORTSC register and observing that the Suspend and Force Port Resume bits
are zero. The software must ensure that the host controller is running (that is, HCHalted bit in the USBSTS
register is a zero), before terminating a resume by clearing the port's Force Port Resume bit. If HCHalted
is a one when Force Port Resume is cleared, then SOFs will not occur down the enabled port and the device
will return to suspend mode in a maximum of 10 milliseconds.
Table 24-63
summarizes the wake-up events. Whenever a resume event is detected, the Port Change
Detect bit in the USBSTS register is set. If the Port Change Interrupt Enable bit is a one in the USBINTR
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor
24-69