MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 580

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Universal Serial Bus Interface
24.9.14.1 Transfer/Transaction Based Interrupts
These interrupt sources are associated with transfer and transaction progress. They are all dependent on
the next interrupt threshold.
24.9.14.1.1 Transaction Error
A transaction error is any error that caused the host controller to think that the transfer did not complete
successfully.
The effects of the error counter and interrupt status are summarized in the following paragraphs. Most of
these errors set the XactErr status bit in the appropriate interface data structure.
There is a small set of protocol errors that relate only when executing a queue head and fit under the
umbrella of a WRONG PID error that are significant to explicitly identify. When these errors occur, the
XactErr status bit in the queue head is set and the Cerr field is decremented. When the PID Code indicates
a SETUP, the following responses are protocol errors and result in XactErr bit being set and the Cerr field
being decremented.
24.9.14.1.2 Serial Bus Babble
When a device transmits more data on the USB than the host controller is expecting for this transaction, it
is defined to be babbling. In general, this is called a Packet Babble. When a device sends more data than
the Maximum Length number of bytes, the host controller sets the Babble Detected bit to a one and halts
24-118
•
•
•
EPS field indicates a high-speed device and it returns a Nak handshake to a SETUP.
EPS field indicates a high-speed device and it returns a Nyet handshake to a SETUP.
EPS field indicates a low- or full-speed device and the complete-split receives a Nak handshake.
1
2
CRC
Timeout
Bad PID
Babble
Buffer Error
If occurs in a queue head, then USBERRINT is asserted only when Cerr counts down from a one to a
zero. In addition the queue is halted.
The host controller received a response from the device, but it could not recognize the PID as a valid PID.
Result
Event/
Table 24-72
The only method the software should use for acknowledging an interrupt is
by transitioning the appropriate status bits in the USBSTS register from a
one to a zero.
2
Cerr
N/A
N/A
-1
-1
-1
lists the events/responses that the host can observe as a result of a transaction.
Queue Head/qTD/iTD/siTD Side Effects
Table 24-72. Summary of Transaction Errors
See
See
Section 24.9.14.1.2, “Serial Bus Babble”
Section 24.9.14.1.3, “Data Buffer Error”
MCF5253 Reference Manual, Rev. 1
Status Field
XactErr set
XactErr set
XactErr set
NOTE
USBSTS[USBERRINT]
1
1
1
Freescale Semiconductor
1
–
1
1
1